© 2004 Microchip Technology Inc. DS70062C-page 15-25
Section 15. Motor Control PWM
Motor Control
PWM
15
The Complementary mode is selected for each PWM I/O pin pair by clearing the appropriate
PMODx bit in PWMCON1. The PWM I/O pins are set to complementary mode by default upon a
device reset.
Figure 15-12: PWM Channel Block Diagram, Complementary Mode
15.6 Dead Time Control
Dead time generation is automatically enabled when any of the PWM I/O pin pairs are operating
in the Complementary Output mode. Because the power output devices cannot switch instanta-
neously, some amount of time must be provided between the turn-off event of one PWM output
in a complementary pair and the turn-on event of the other transistor.
The 6-output PWM module has one programmable dead time. The 8-output PWM module
allows two different dead times to be programmed. These two dead times may be used in one
of two methods described below to increase user flexibility:
• The PWM output signals can be optimized for different turn-off times in the high-side and
low-side transistors. The first dead time is inserted between the turn-off event of the lower
transistor of the complementary pair and the turn-on event of the upper transistor. The
second dead time is inserted between the turn-off event of the upper transistor and the
turn-on event of the lower transistor.
• The two dead times can be assigned to individual PWM I/O pin pairs. This operating mode
allows the PWM module to drive different transistor/load combinations with each
complementary PWM I/O pin pair.
15.6.1 Dead Time Generators
Each complementary output pair for the PWM module has a 6-bit down counter that is used to
produce the dead time insertion. As shown in Figure 15-13, each dead time unit has a rising
and falling edge detector connected to the duty cycle comparison output.
One of the two possible dead times is loaded into the timer on the detected PWM edge event.
Depending on whether the edge is rising or falling, one of the transitions on the complementary
outputs is delayed until the timer counts down to zero. A timing diagram indicating the dead time
insertion for one pair of PWM outputs is shown in Figure 15-14. The use of two different dead
times for the rising and falling edge events has been exaggerated in the figure for clarity.
Dead
Time
Generator
PWM Generator
PWMxH
PWMxL
Override
and
Fault Logic
To Next Page
Loading...
