© 2004 Microchip Technology Inc. DS70049C-page 2-27
Section 2. CPU
CPU
2
2.7 Divide Support
The dsPIC30F supports the following types of division operations:
• DIVF: 16/16 signed fractional divide
• DIV.SD: 32/16 signed divide
• DIV.UD: 32/16 unsigned divide
• DIV.SW: 16/16 signed divide
• DIV.UW: 16/16 unsigned divide
The quotient for all divide instructions is placed in W0, and the remainder in W1. The 16-bit
divisor can be located in any W register. A 16-bit dividend can be located in any W register and
a 32-bit dividend must be located in an adjacent pair of W registers.
All divide instructions are iterative operations and must be executed 18 times within a REPEAT
loop. The user is responsible for programming the REPEAT instruction. A complete divide
operation takes 19 instruction cycles to execute.
The divide flow is interruptible, just like any other REPEAT loop. All data is restored into the
respective data registers after each iteration of the loop, so the user will be responsible for
saving the appropriate W registers in the ISR. Although they are important to the divide
hardware, the intermediate values in the W registers have no meaning to the user. The divide
instructions must be executed 18 times in a REPEAT loop to produce a meaningful result.
Refer to the “dsPIC30F Programmer’s Reference Manual” (DS70030) for more information and
programming examples for the divide instructions.
2.8 Instruction Flow Types
Most instructions in the dsPIC30F architecture occupy a single word of program memory and
execute in a single cycle. An instruction pre-fetch mechanism facilitates single cycle (1 T
CY)
execution. However, some instructions take 2 or 3 instruction cycles to execute. Consequently,
there are seven different types of instruction flow in the dsPIC
®
architecture. These are described
below:
1. 1 Instruction Word, 1 Instruction Cycle:
These instructions will take one instruction cycle to execute as shown in Figure 2-12. Most
instructions are 1-word, 1-cycle instructions.
Figure 2-12: Instruction Flow – 1-Word, 1-Cycle
2. 1 Instruction Word, 2 Instruction Cycles:
In these instructions, there is no pre-fetch flush. The only instructions of this type are the
MOV.D instructions (load and store double-word). Two cycles are required to complete these
instructions, as shown in Figure 2-13.
Figure 2-13: Instruction Flow – 1-Word, 2-Cycle (MOV.D Operation)
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOV #0x55AA,W0 Fetch 1 Execute 1
2. MOV W0,PORTA Fetch 2 Execute 2
3. MOV W0,PORTB Fetch 3 Execute 3
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOV #0x1234,W0 Fetch 1 Execute 1
2. MOV.D [W0++],W1 Fetch 2 Execute 2
R/W Cycle 1
3. MOV #0x00AA,W1 Fetch 3 Execute 2
R/W Cycle2
No Fetch Execute 3
4. MOV #0x00CC,W0 Fetch 4 Execute 4
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