dsPIC30F Family Reference Manual
DS70049C-page 2-26 © 2004 Microchip Technology Inc.
2.6.5 Barrel Shifter
The barrel shifter is capable of performing up to a 16-bit arithmetic right shift, or up to a 16-bit left
shift, in a single cycle. The barrel shifter can be used by DSP instructions or MCU instructions for
multi-bit shifts.
The shifter requires a signed binary value to determine both the magnitude (number of bits) and
direction of the shift operation:
• A positive value will shift the operand right
• A negative value will shift the operand left
• A value of ‘0’ will not modify the operand
The barrel shifter is 40-bits wide to accommodate the width of the accumulators. A 40-bit output
result is provided for DSP shift operations, and a 16-bit result for MCU shift operations.
A summary of instructions that use the barrel shifter is provided below in Table 2-6.
Table 2-6: Instructions that Utilize the DSP Engine Barrel Shifter
2.6.6 DSP Engine Mode Selection
The various operational characteristics of the DSP engine discussed in previous sub-sections
can be selected through the CPU Core Configuration register (CORCON). These are listed
below:
• Fractional or integer multiply operation.
• Conventional or convergent rounding.
• Automatic saturation on/off for ACCA.
• Automatic saturation on/off for ACCB.
• Automatic saturation on/off for writes to data memory.
• Accumulator Saturation mode selection.
2.6.7 DSP Engine Trap Events
The various arithmetic error traps that can be generated for handling exceptions in the DSP
engine are selected through the Interrupt Control register (INTCON1). These are listed below:
• Trap on ACCA overflow enable, using OVATE (INTCON1<10>).
• Trap on ACCB overflow enable, using OVBTE (INTCON1<9>).
• Trap on catastrophic ACCA and/or ACCB overflow enable, using COVTE (INTCON1<8>).
An arithmetic error trap will also be generated when the user attempts to shift a value beyond the
maximum allowable range (+/- 16 bits) using the SFTAC instruction. This trap source cannot be
disabled. The execution of the instruction will complete, but the results of the shift will not be
written to the target accumulator.
For further information on bits in the INTCON1 register and arithmetic error traps, please refer to
Section 6. “Reset Interrupts”.
Instruction Description
ASR Arithmetic multi-bit right shift of data memory location
LSR Logical multi-bit right shift of data memory location
SL Multi-bit shift left of data memory location
SAC Store DSP accumulator with optional shift
SFTAC Shift DSP accumulator
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