dsPIC30F Family Reference Manual
DS70057C-page 10-2 © 2004 Microchip Technology Inc.
10.1 Introduction
This section addresses the Watchdog Timer (WDT) and Power Saving modes of the dsPIC30F
device family. The dsPIC devices have two reduced Power modes that can be entered through
execution of the PWRSAV instruction:
• Sleep Mode: The CPU, system clock source, and any peripherals that operate on the
system clock source are disabled. This is the lowest Power mode for the device.
• Idle Mode: The CPU is disabled, but the system clock source continues to operate.
Peripherals continue to operate, but can optionally be disabled.
The WDT, when enabled, operates from the internal LPRC clock source and can be used to
detect system software malfunctions by resetting the device if the WDT has not been cleared in
software. Various WDT time-out periods can be selected using the WDT postscaler. The WDT
can also be used to wake the device from Sleep or Idle mode.
10.2 Power Saving Modes
The dsPIC30F device family has two special Power Saving modes, Sleep mode and Idle mode,
that can be entered through the execution of a special PWRSAV instruction.
The assembly syntax of the PWRSAV instruction is as follows:
PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode
PWRSAV #IDLE_MODE ; Put the device into IDLE mode
The Power Saving modes can be exited as a result of an enabled interrupt, WDT time-out, or a
device Reset. When the device exits one of these two Operating modes, it is said to ‘wake-up’.
The characteristics of the Power Saving modes are described in subsequent sections.
10.3 Sleep Mode
The characteristics of Sleep mode are as follows:
• The system clock source is shutdown. If an on-chip oscillator is used, it is turned off.
• The device current consumption will be at a minimum provided that no I/O pin is sourcing
current.
• The Fail-Safe Clock Monitor (FSCM) does not operate during Sleep mode since the system
clock source is disabled.
• The LPRC clock will continue to run in Sleep mode if the WDT is enabled.
• The Low Voltage Detect circuit, if enabled, remains operative during Sleep mode.
• The BOR circuit, if enabled, remains operative during Sleep mode.
• The WDT, if enabled, is automatically cleared prior to entering Sleep mode.
• Some peripherals may continue to operate in Sleep mode. These peripherals include I/O
pins that detect a change in the input signal, or peripherals that use an external clock input.
Any peripheral that is operating on the system clock source will be disabled in Sleep mode.
The processor will exit, or ‘wake-up’, from Sleep on one of the following events:
• On any interrupt source that is individually enabled
• On any form of device Reset
• On a WDT time-out
10.3.1 Clock Selection on Wake-up from Sleep
The processor will restart the same clock source that was active when Sleep mode was entered.
Note: SLEEP_MODE and IDLE_MODE are constants defined in the assembler include
file for the selected device.
To Next Page
Loading...
