© 2004 Microchip Technology Inc. DS70060C-page 13-9
Section 13. Input Capture
Input Capture
13
13.5.1 Input Capture Buffer Not Empty (ICBNE)
The ICBNE read only Status bit (ICxCON<3>) will be set on the first input capture event and
remain set until all capture events have been read from the capture buffer. For example, if three
capture events have occurred, then three reads of the capture buffer are required before the
ICBNE (ICxCON<3>) flag will be cleared. If four capture events, then four reads are required to
clear the ICBNE (ICxCON<3>) flag. Each read of the capture buffer will allow the remaining
word(s) to move to the next available top location. Since the ICBNE reflects the capture buffer
state, the ICBNE Status bit will be cleared in the event of any device Reset.
13.5.2 Input Capture Overflow (ICOV)
The ICOV read only Status bit (ICxCON<4>) will be set when the capture buffer overflows. In the
event that buffer is full with four capture events and a fifth capture event occurs prior to a read of
the buffer, an overrun condition will occur, the ICOV (ICxCON<4>) bit will be set to a logic ‘1’ and
the respective capture event interrupt will not be generated. In addition, the fifth capture event is
not recorded and all subsequent capture events will not alter the current buffer contents.
To clear the overrun condition, the capture buffer must be read four times. Upon the fourth read,
the ICOV (ICxCON<4>) status flag will be cleared and the capture channel will resume normal
operation.
Clearing of the overflow condition can be accomplished in the following ways:
• Set ICM<2:0> (ICxCON<2:0>) = 000
• Read capture buffer until ICBNE (ICxCON<3>) = 0
• Any device Reset
13.5.2.1 ICOV and Interrupt Only Mode
The input capture module can also be configured to function as an external interrupt pin. For this
mode, the ICI<1:0> (ICxCON<6:5>) bits must be set to ‘00’. Interrupts will be generated
independently of buffer reads.
13.6 Input Capture Interrupts
The input capture module has the ability to generate an interrupt based upon a selected number
of capture events. A capture event is defined as a write of a time base value into the capture
buffer. This setting is configured by the control bits ICI<1:0> (ICxCON<6:5>).
Except for the case when ICI<1:0> = ‘00’, no interrupts will be generated until a buffer overflow
condition is removed (see Section 13.5.2 “Input Capture Overflow (ICOV)”). When the
capture buffer has been emptied, either by a Reset condition or a read operation, the interrupt
count is reset. This allows for the resynchronization of the interrupt count to the FIFO entry
status.
13.6.1 Interrupt Control Bits
Each input capture channel has interrupt flag Status bits (ICxIF), interrupt enable bits (ICxIE) and
interrupt priority control bits (ICxIP<2:0>). Refer to Section 6. “Reset Interrupts” for further
information on peripheral interrupts.
13.7 UART Autobaud Support
The input capture module can be used by the UART module when the UART is configured for
the Autobaud mode of operation, ABAUD = 1 (UxMODE<5>). When the ABAUD control bit is set,
the UART RX pin will be internally connected to the assigned input capture module input. The
I/O pin associated with the capture module will be disconnected. The baud rate can be deter-
mined by measuring the width of the Start bit when a NULL character is received. Note that the
capture module must be configured for the Edge Detection mode (capture on every rising and
falling edge) to take advantage of the autobaud feature. The input capture module assignment
for each UART will depend on the dsPIC30F device variant that is selected. Refer to the device
data sheet for further details on the autobaud support.
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