Microchip Technology dsPIC30F - Device Start-Up Time Lines

© 2004 Microchip Technology Inc. DS70055C-page 8-13
Section 8. Reset
Reset
8
8.10 Device Start-up Time Lines
Figure 8-5 through Figure 8-8 show graphical time lines of the delays associated with device
Reset for several operating scenarios.
Figure 8-5 shows the delay time line when a crystal oscillator and PLL are used as the system
clock and the PWRT is disabled. The internal Power-on Reset pulse occurs at the V
POR
threshold. A small POR delay occurs after the internal Reset pulse. (The POR delay is always
inserted before device operation begins.)
The FSCM, if enabled, begins to monitor the system clock for activity when the FSCM delay
expires. Figure 8-5 shows that the oscillator and PLL delays expire before the Fail-Safe Clock
Monitor (FSCM) is enabled. However, it is possible that these delays may not expire until after
FSCM is enabled. In this case, the FSCM would detect a clock failure and a clock failure trap
will be generated. If the FSCM delay does not provide adequate time for the oscillator and PLL
to stabilize, the PWRT could be enabled to allow more delay time before device operation
begins and the FSCM starts to monitor the system clock.
Figure 8-5: Device Reset Delay, Crystal + PLL Clock Source, PWRT Disabled
POR Circuit Threshold Voltage
SYSRST
Oscillator
Internal Power-on Reset Pulse
TPOR
TFSCM
TOST
TLOCK
VDD
Oscillator released to system, device operation
POR
System Reset released.
Note 1: Delay times shown are not drawn to scale.
2: FSCM, if enabled, monitors system clock at expiration of T
POR + TFSCM.
3: T
LOCK not inserted when PLL is disabled.
FSCM
FSCM enabled.
begins.
OSC Delay
System OSC