Microchip Technology dsPIC30F - Page 206

dsPIC30F Family Reference Manual
DS70055C-page 8-14 © 2004 Microchip Technology Inc.
The Reset time line shown in Figure 8-6 is similar to that shown in Figure 8-5, except that the
PWRT has been enabled to increase the amount of delay time before SYSRST
is released.
The FSCM, if enabled, will begin to monitor the system clock after T
FSCM expires. Note that the
additional PWRT delay time added to T
FSCM provides ample time for the system clock source to
stabilize in most cases.
Figure 8-6: Device Reset Delay, Crystal + PLL Clock Source, PWRT Enabled
POR Circuit Threshold Voltage
SYSRST
Internal Power-on Reset Pulse
TPOR
TPWRT
TOST
TLOCK
VDD
Oscillator released to system.
POR
Note 1: Delay times shown are not drawn to scale.
2: FSCM, if enabled, monitors system clock at expiration of T
POR + TPWRT + TFSCM.
3: T
LOCK not inserted when PLL is is disabled.
TFSCM short
compared to
T
PWRT.
FSCM
Device operation
begins.
OSC Delay
TFSCM