© 2004 Microchip Technology Inc. DS70055C-page 8-15
Section 8. Reset
Reset
8
The Reset time line in Figure 8-7 shows an example when an EC + PLL clock source is used as
the system clock and the PWRT is enabled. This example is similar to the one shown in
Figure 8-6, except that the oscillator start-up timer delay, T
OST, does not occur.
Figure 8-7: Device Reset Delay, EC + PLL Clock, PWRT Enabled
POR Circuit Threshold Voltage
SYSRST
Internal Power-on Reset Pulse
TPOR
TPWRT
TLOCK
VDD
POR
Note 1: Delay times shown are not drawn to scale.
2: FSCM, if enabled, monitors system clock at expiration of T
POR + TPWRT + TFSCM.
3: T
LOCK not inserted when PLL is is disabled.
TFSCM short
compared to
T
PWRT.
FSCM
Device operation
begins.
OSC Delay
TFSCM
Oscillator released to system.
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