dsPIC30F Family Reference Manual
DS70054C-page 7-22 © 2004 Microchip Technology Inc.
Figure 7-13: Postscaler Update Timing
7.17 Clock Switching Operation
The selection of clock sources available for clock switching during device operation are as
follows:
• Primary oscillator on OSC1/OSC2 pins
• Low Power 32 kHz Crystal (Secondary) oscillator on SOSCO/SOSCI pins
• Internal Fast RC (FRC) oscillator
• Internal Low Power RC (LPRC) oscillator
7.17.1 Clock Switching Enable
To enable clock switching, the FCKSM1 configuration bit in the FOSC Configuration register must
be programmed to a ‘0’. (Refer to Section 24. “Device Configuration” for further details.)
If the FCKSM1 configuration bit is a ‘1’ (unprogrammed), then the clock switching function is
disabled. The Fail-Safe Clock Monitor function is also disabled. This is the default setting. The
NOSC<1:0> control bits (OSCCON<9:8>) do not control the clock selection when clock switching
is disabled. However, the COSC<1:0> bits (OSCCON<13:12>) will reflect the clock source
selected by the FPR<3:0> and FOS<1:0> configuration bits in the F
OSC Configuration register.
The OSWEN control bit (OSCCON<0>) has no effect when clock switching is disabled. It is held
at ‘0’ at all times.
Divide
by 4
Divide
by 16
Divide
by 64
POST<1:0>
00
01
10
11
Postscaled
System
Clock
System
1:4 1:16 1:1
1:64
Clock
Note: This diagram demonstrates the clock postscaler function only. The divide ratios shown in the timing diagram
are not correct.
Note: The Primary oscillator has multiple Operating modes (EC, RC, XT, etc.). The
Operating mode of the Primary oscillator is determined by the FPR<3:0>
configuration bits in the FOSC device configuration register. (Refer to Section
24. “Device Configuration” for further details.)
To Next Page
Loading...
