Microchip Technology dsPIC30F - Page 187

© 2004 Microchip Technology Inc. DS70054C-page 7-23
Section 7. Oscillator
Oscillator
7
7.17.2 Oscillator Switching Sequence
The following steps are taken by the hardware and software to change the device clock source:
1. Read the COSC<1:0> status bits (OSCCON<13:12>), if desired, to determine current
oscillator source.
2. Perform the unlock sequence to allow a write to the OSCCON register high byte.
3. Write the appropriate value to the NOSC<1:0> control bits (OSCCON<9:8>) for the new
oscillator source.
4. Perform the unlock sequence to allow a write to the OSCCON register low byte.
5. Set the OSWEN bit (OSCCON<0>). This will INITIATE the oscillator switch.
6. The clock switching hardware compares the COSC<1:0> status bits with the new value of
the NOSC<1:0> control bits. If they are the same, then the clock switch is a redundant
operation. In this case, the OSWEN bit is cleared automatically and the clock switch is
aborted.
7. If a valid clock switch has been initiated, the LOCK (OSCCON<5>) and the CF
(OSCCON<3>) status bits are cleared.
8. The new oscillator is turned on by the hardware if it is not currently running. If a crystal
oscillator must be turned on, the hardware will wait until the OST expires. If the new
source is using the PLL, then the hardware waits until a PLL lock is detected (LOCK = 1).
9. The hardware waits for 10 clock cycles from the new clock source and then performs the
clock switch.
10. The hardware clears the OSWEN bit to indicate a successful clock transition. In addition,
the NOSC<1:0> bit values are transferred to the COSC<1:0> status bits.
11. The clock switch is completed. The old clock source will be turned off at this time, with the
following exceptions:
• The LPRC oscillator will stay on if the WDT or FSCM is enabled.
• The LP oscillator will stay on if LPOSCEN = 1 (OSCCON<1>).
Figure 7-14: Clock Transition Timing Diagram
Note: The processor will continue to execute code throughout the clock switching
sequence. Timing sensitive code should not be executed during this time.
Old Clock Source
New Clock Source
System Clock
Both Oscillators Active
OSWEN
1 2 3 4 5 6 7 8 9 10
New Source
Enabled
New Source
Stable
Old Source
Disabled
Note: The system clock can be any selected source – Primary, Secondary, FRC or LPRC.