dsPIC30F Family Reference Manual
DS70054C-page 7-24 © 2004 Microchip Technology Inc.
7.17.3 Clock Switching Tips
• If the destination clock source is a crystal oscillator, the clock switch time will be dominated
by the oscillator start-up time.
• If the new clock source does not start, or is not present, then the clock switching hardware
will simply wait for the 10 synchronization cycles to occur. The user can detect this situation
because the OSWEN bit (OSCCON<0>) remains set indefinitely.
• If the new clock source uses the PLL, a clock switch will not occur until lock has been
achieved. The user can detect a loss of PLL lock because the LOCK bit will be cleared and
the OSWEN bit is set.
• The user may wish to consider the settings of the POST<1:0> control bits (OSCCON<7:6>)
when executing a clock switch. Switching to a low frequency clock source, such as the LP
oscillator with a postscaler ratio greater than 1:1, will result in very slow device operation.
7.17.4 Aborting a Clock Switch
In the event the clock switch did not complete, the clock switch logic can be reset by clearing the
OSWEN bit. Clearing the OSWEN bit (OSCCON<0>) will:
1. Abandon the clock switch
2. Stop and reset the OST, if applicable
3. Stop the PLL, if applicable
A clock switch procedure can be aborted at any time.
7.17.5 Entering Sleep Mode During a Clock Switch
If the device enters Sleep mode during a clock switch operation, the clock switch operation is
aborted. The processor keeps the old clock selection and the OSWEN bit is cleared. The PWRSAV
instruction is then executed normally.
7.17.6 Recommended Code Sequence for Clock Switching
The following steps should be taken to change the oscillator source:
• Disable interrupts during the OSCCON register unlock and write sequence.
• Execute unlock sequence for OSCCON high byte.
• Write new oscillator source to NOSC<1:0> control bits.
• Execute unlock sequence for OSCCON low byte.
• Set OSWEN bit.
• Continue to execute code that is not clock sensitive (optional).
• Invoke an appropriate amount of software delay (cycle counting) to allow for oscillator
and/or PLL start-up.
• Check to see if OSWEN is ‘0’. If it is, we are DONE SUCCESSFULLY.
• If OSWEN is still set, then check LOCK bit to determine cause of failure.
Note: The application should not attempt to switch to a clock of frequency lower than
100 KHz when the fail-safe clock monitor is enabled. If such clock switching is
performed, the device may generate an oscillator fail trap and switch to the Fast RC
oscillator.
To Next Page
Loading...
