Microchip Technology dsPIC30F - Bit-Reversed Addressing

dsPIC30F Family Reference Manual
DS70050C-page 3-14 © 2004 Microchip Technology Inc.
3.4 Bit-Reversed Addressing
3.4.1 Introduction to Bit-Reversed Addressing
Bit-reversed addressing simplifies data re-ordering for radix-2 FFT algorithms. It is supported
through the X WAGU only. Bit-reversed addressing is accomplished by effectively creating a
‘mirror image’ of an address pointer by swapping the bit locations around the center point of the
binary value, as shown in Figure 3-7. An example bit-reversed sequence for a 4-bit address field
is shown in Table 3-1.
Figure 3-7: Bit-Reversed Address Example
Table 3-1: Bit-Reversed Address Sequence (16-Entry)
b3 b2 b1 b0
b0 b1 b2 b3
Bit locations swapped left-to-right
around center of binary value.
Bit-Reversed Result
Normal
Address
Bit-Reversed
Address
A3 A2 A1 A0 decimal A3 A2 A1 A0 decimal
0000 0 0000 0
0001 1 1000 8
0010 2 0100 4
0011 3 1100 12
0100 4 0010 2
0101 5 1010 10
0110 6 0110 6
0111 7 1110 14
1000 8 0001 1
1001 9 1001 9
1010 10 0101 5
1011 11 1101 13
1100 12 0011 3
1101 13 1011 11
1110 14 0111 7
1111 15 1111 15