© 2004 Microchip Technology Inc. DS70055C-page 8-7
Section 8. Reset
Reset
8
8.3.1 Using the POR Circuit
To take advantage of the POR circuit, just tie the MCLR pin directly to VDD. This will eliminate
external RC components usually needed to create a Power-on Reset delay. A minimum rise time
for V
DD is required. Refer to the “Electrical Specifications” section in the specific device data
sheet for further details.
Depending on the application, a resistor may be required between the MCLR
pin and VDD. This
resistor can be used to decouple the MCLR
pin from a noisy power supply rail. The resistor will
also be necessary if the device programming voltage, V
PP, needs to be placed on the MCLR pin
while the device is installed in the application circuit. V
PP is 13 volts for most devices.
Figure 8-3 shows a possible POR circuit for a slow power supply ramp up. The external
Power-on Reset circuit is only required if the device would exit Reset before the device V
DD is in
the valid operating range. The diode, D, helps discharge the capacitor quickly when V
DD powers
down.
Figure 8-3: External Power-on Reset Circuit (For Slow V
DD Rise Time)
8.3.2 Power-up Timer (PWRT)
The PWRT provides an optional time delay (TPWRT) before SYSRST is released at a device POR
or BOR (Brown-out Reset). The PWRT time delay is provided in addition to the POR delay time
(T
POR). The PWRT time delay may be 0 ms, 4 ms, 16 ms or 64 ms nominal (see Figure 8-2).
The PWRT delay time is selected using the FPWRT<1:0> configuration fuses in the FBORPOR
Device Configuration register. Refer to Section 24. “Device Configuration” for further details.
8.4 External Reset (EXTR)
Whenever the MCLR pin is driven low, the device will asynchronously assert SYSRST, provided
the input pulse on MCLR
is longer than a certain minimum width. (Refer to the “Electrical
Specifications” in the specific device data sheet for further details.) When the MCLR
pin is
released, SYSRST
will be released on the next instruction clock cycle, and the Reset vector fetch
will commence. The processor will maintain the existing clock source that was in use before the
EXTR occurred. The EXTR status bit (RCON<7>) will be set to indicate the MCLR
Reset.
8.5 Software RESET Instruction (SWR)
Whenever the RESET instruction is executed, the device will assert SYSRST, placing the device
in a special Reset state. This Reset state will not re-initialize the clock. The clock source in effect
prior to the RESET instruction will remain. S
YSRST will be released at the next instruction cycle,
and the Reset vector fetch will commence.
8.6 Watchdog Time-out Reset (WDTR)
Whenever a Watchdog time-out occurs, the device will asynchronously assert SYSRST. The
clock source will remain unchanged. Note that a WDT time-out during Sleep or Idle mode will
wake-up the processor, but NOT reset the processor. For more information, refer to Section
10. “Watchdog Timer and Power Saving Modes”.
Note 1: The value of R should be low enough so that the voltage drop across it does not violate
the V
IH specification of the MCLR pin.
2: R1 will limit any current flowing into MCLR
from external capacitor C in the event of
MCLR
/VPP pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress
(EOS).
R1
MCLR
dsPIC30F
R
D
C
V
DD
VDD
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