dsPIC30F Family Reference Manual
DS70055C-page 8-6 © 2004 Microchip Technology Inc.
Figure 8-2: POR Module Timing Diagram for Rising VDD
TPOR
VDDPOR Circuit
Time
Time
V
POR
POR Circuit Threshold Voltage
SYSRST
Time
TPWRT
Internal Power-on Reset pulse occurs at VPOR
and begins POR delay time, TPOR.
POR circuit is initialized at V
POR.
System Reset is released
after Power-up Timer
expires.
(0 ms, 4 ms, 16 ms or 64 ms)
Note: When the device exits the Reset condition (begins normal operation), the device
operating parameters (voltage, frequency, temperature, etc.) must be within their
operating ranges, otherwise the device will not function correctly. The user must
ensure that the delay between the time power is first applied and the time SYSRST
becomes inactive is long enough to get all operating parameters within
specification.
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