© 2004 Microchip Technology Inc. DS70055C-page 8-5
Section 8. Reset
Reset
8
8.2 Clock Source Selection at Reset
If clock switching is enabled, the system clock source at device Reset is chosen as shown in
Table 8-1. If clock switching is disabled, the system clock source is always selected according to
the oscillator configuration fuses. Refer to Section 7. “Oscillator” for further details.
Table 8-1: Oscillator Selection vs. Type of Reset (Clock Switching Enabled)
8.3 POR: Power-on Reset
There are two threshold voltages associated with a Power-on Reset (POR). The first voltage is
the device threshold voltage, V
POR. The device threshold voltage is the voltage at which the
device logic circuits become operable. The second voltage associated with a POR event is the
POR circuit threshold voltage which is nominally 1.85V.
A power-on event will generate an internal Power-on Reset pulse when a V
DD rise is detected.
The Reset pulse will be generated at V
POR. The device supply voltage characteristics must meet
specified starting voltage and rise rate requirements to generate the POR pulse. In particular,
V
DD must fall below VPOR before a new POR is initiated. For more information on the VPOR and
the V
DD rise rate specifications, please refer to the “Electrical Specifications” section of the
device data sheet.
The POR pulse will reset a POR timer and place the device in the Reset state. The POR also
selects the device clock source identified by the oscillator configuration bits.
After the Power-on Reset pulse is generated, the POR circuit inserts a small delay, T
POR, which
is nominally 10 µs and ensures that internal device bias circuits are stable. Furthermore, a user
selected Power-up Time-out (T
PWRT) may be applied. The TPWRT parameter is based on device
configuration bits and can be 0 ms (no delay), 4 ms, 16 ms or 64 ms. The total delay time at
device power-up is T
POR + TPWRT. When these delays have expired, SYSRST will be released
on the next leading edge of the instruction cycle clock, and the PC will jump to the Reset vector.
The timing for the SYSRST
signal is shown in Figure 8-2. A Power-on Reset is initialized when
V
DD
falls below a threshold voltage, VT. The POR delay time is inserted when VDD crosses the
POR circuit threshold voltage. Finally, the PWRT delay time, T
PWRT, is inserted before SYSRST
is released.
The power-on event will set the POR and BOR status bits (RCON<1:0>).
Reset Type Clock Source Selected Based On
POR Oscillator Configuration Fuses
BOR Oscillator Configuration Fuses
EXTR COSC Control bits (OSCCON<13:12>)
WDTR COSC Control bits (OSCCON<13:12>)
SWR COSC Control bits (OSCCON<13:12>)
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