Microchip Technology dsPIC30F - Communicating as a Slave

dsPIC30F Family Reference Manual
DS70068C-page 21-32 © 2004 Microchip Technology Inc.
21.7 Communicating as a Slave
In some systems, particularly where multiple processors communicate with each other, the
dsPIC30F device may communicate as a slave (see Figure 21-21). When the module is
enabled, the slave module is active. The slave may not initiate a message, it can only respond
to a message sequence initiated by a master. The master requests a response from a particular
slave as defined by the device address byte in the I
2
C protocol. The slave module replies to the
master at the appropriate times as defined by the protocol.
As with the master module, sequencing the components of the protocol for the reply is a
software task. However, the slave module detects when the device address matches the
address specified by the software for that slave.
Figure 21-21: A Typical Slave I
2
C Message: Multiprocessor Command/Status
After a Start condition, the slave module will receive and check the device address. The slave
may specify either a 7-bit address or a 10-bit address. When a device address is matched, the
module will generate an interrupt to notify the software that its device is selected. Based on the
R/W
bit sent by the master, the slave will either receive or transmit data. If the slave is to receive
data, the slave module automatically generates the Acknowledge (ACK
), loads the I2CRCV
register with the received value currently in the I2CRSR register and notifies the software
through an interrupt. If the slave is to transmit data, the software must load the I2CTRN register.
21.7.1 Sampling Receive Data
All incoming bits are sampled with the rising edge of the clock (SCL) line.
21.7.2 Detecting Start and Stop Conditions
The slave module will detect Start and Stop conditions on the bus and indicate that status on the
S bit (I2CSTAT<3>) and P bit (I2CSTAT<4>). The Start (S) and Stop (P) bits are cleared when a
Reset occurs or when the module is disabled. After detection of a Start or Repeated Start event,
the S bit is set and the P bit is cleared. After detection of a Stop event, the P bit is set and the S
bit is clear.
Bus
Master
SDA
A
C
K
N
A
C
A
C
K
A
C
K
A
C
K
S
T
O
P
S
T
A
R
T
First
Address
Second
Address
Command
Data
Address
Byte
Status
Data
S
T
A
R
T
S
AAA
0
210
R 1111
AA
1
98
P
K
Slave
SDA
Activity
N
AAAA
R
E
R
R
/
W
R
/
W
Output
Output
A
3
A
4
A
5
A
6
A
7
A
8
A
9
01111
0
ByteByteByte Byte
10-bit
Address