Microchip Technology dsPIC30F - Page 547

© 2004 Microchip Technology Inc. DS70068C-page 21-33
Section 21. Inter-Integrated Circuit (I
2
C)
Inter-Integrated
Circuit (I
2
C)
21
21.7.3 Detecting the Address
Once the module has been enabled, the slave module waits for a Start condition to occur. After
a Start, depending on the A10M bit (I2CCON<10>), the slave will attempt to detect a 7-bit or
10-bit address. The slave module will compare 1 received byte for a 7-bit address or 2 received
bytes for a 10-bit address. A 7-bit address also contains a R/W
bit that specifies the direction of
data transfer after the address. If R/W
= 0, a write is specified and the slave will receive data
from the master. If R/W
= 1, a read is specified and the slave will send data to the master. The
10-bit address contains a R/W
bit, however by definition, it is always R/W = 0 because the slave
must receive the second byte of the 10-bit address.
21.7.3.1 7-bit Address and Slave Write
Following the Start condition, the module shifts 8 bits into the I2CRSR register (see
Figure 21-22). The value of register I2CRSR<7:1> is compared to the value of the
I2CADD<6:0> register. The device address is compared on the falling edge of the eighth clock
(SCL). If the addresses match, the following events occur:
1. An ACK
is generated.
2. The D_A and R_W bits are cleared.
3. The module generates the SI2CIF interrupt on the falling edge of the ninth SCL clock.
4. The module will wait for the master to send data.
Figure 21-22: Slave Write 7-bit Address Detection Timing Diagram
SCL (Master)
SDA (Master)
SDA (Slave)
SI2CIF Interrupt
3 41 2
- Detecting Start bit enables
1
I
2
C Bus State
(S) (D) (D)
(A)(D) (Q)
A4A5A6 A3 A2 A1 A0
R/W
D_A
ADD10
SCLREL
R_W
address detection.
- R/W
= 0 bit indicates that slave
2
receives data bytes.
- Address match of first byte clears
3
D_A bit. Slave generates ACK
.
- R_W bit cleared. Slave generates
4
interrupt.
5
- Bus waiting. Slave ready to
5
receive data.
=0