© 2004 Microchip Technology Inc. DS70066C-page 19-3
Section 19. UART
UART
19
19.2 Control Registers
Register 19-1: UXMODE: UARTX Mode Register
Upper Byte:
R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 U-0 U-0
UARTEN
—USIDL— reserved ALTIO reserved reserved
bit 15 bit 8
Lower Byte:
R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
WAKE LPBACK ABAUD
— —PDSEL<1:0>STSEL
bit 7 bit 0
bit 15 UARTEN: UART Enable bit
1 = UART is enabled. UART pins are controlled by UART as defined by UEN<1:0> and UTXEN control bits.
0 = UART is disabled. UART pins are controlled by corresponding PORT, LAT, and TRIS bits.
bit 14 Unimplemented: Read as ‘0’
bit 13 USIDL: Stop in Idle Mode bit
1 = Discontinue operation when device enters Idle mode
0 = Continue operation in Idle mode
bit 12 Unimplemented: Read as ‘0’
bit 11 Reserved: Write ‘0’ to this location
bit 10 ALTIO: UART Alternate I/O Selection bit
1 = UART communicates using UxATX and UxARX I/O pins
0 = UART communicates using UxTX and UxRX I/O pins
Note: The alternate UART I/O pins are not available on all devices. See device data sheet for details.
bit 9-8 Reserved: Write ‘0’ to these locations
bit 7 WAKE: Enable Wake-up on Start bit Detect During Sleep Mode bit
1 = Wake-up enabled
0 = Wake-up disabled
bit 6 LPBACK: UART Loopback Mode Select bit
1 = Enable Loopback mode
0 = Loopback mode is disabled
bit 5 ABAUD: Auto Baud Enable bit
1 = Input to Capture module from UxRX pin
0 = Input to Capture module from ICx pin
bit 4-3 Unimplemented: Read as ‘0’
bit 2-1 PDSEL<1:0>: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0 STSEL: Stop Selection bit
1 = 2 Stop bits
0 = 1 Stop bit
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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