Microchip Technology dsPIC30F - PWM Time Base

dsPIC30F Family Reference Manual
DS70062C-page 15-16 © 2004 Microchip Technology Inc.
15.3 PWM Time Base
The PWM time base is provided by a 15-bit timer with a prescaler and postscaler (see
Figure 15-2). The 15 bits of the time base are accessible via the PTMR register. PTMR<15> is a
read-only status bit, PTDIR, that indicates the present count direction of the PWM time base. If
the PTDIR status bit is cleared, PTMR is counting upwards. If PTDIR is set, PTMR is counting
downwards.
The time base is enabled/disabled by setting/clearing the PTEN bit (PTCON<15>). PTMR is not
cleared when the PTEN bit is cleared in software.
Figure 15-2: PWM Time Base Block Diagram
The PWM time base can be configured for four different modes of operation:
1. Free Running mode
2. Single Event mode
3. Continuous Up/Down Count mode
4. Continuous Up/Down Count mode with interrupts for double-updates.
These four modes are selected by the PTMOD<1:0> control bits (PTCON<1:0>).
PTMR Register
Time Base period register
Comparator
PTPER
Zero detect
Zero match
Period match
PTMOD1
Up/Down
Timer reset
TCY
Prescaler
1:1, 1:4, 1:16, 1:64
Timer
Direction
Control
Clock
Control
Period load
Duty cycle load
PTMOD1
Period match
Zero match
PTMR clock
Interrupt
Control
PTMOD1
Period
match
Zero
match
PTMOD0
Postscaler
1:1-1:16
PTMOD0
PTEN
PTIF
Update disable (UDIS)
PTDIR (PTMR<15>)
Gated
Gated
Period load
Note: The mode of the PWM time base determines the type of PWM signal that is
generated by the module. (See Section 15.4.2, Section 15.4.3 and Section 15.4.4
for more details.)