Microchip Technology dsPIC30F - Page 327

© 2004 Microchip Technology Inc. DS70062C-page 15-17
Section 15. Motor Control PWM
Motor Control
PWM
15
15.3.1 Free Running Mode
In the Free Running mode, the time base will count upwards until the value in the PTPER
register is matched. The PTMR register is reset on the following input clock edge and the time
base will continue counting upwards as long as the PTEN bit remains set.
15.3.2 Single-Event Mode
In the Single Event Counting mode, the PWM time base will begin counting upwards when the
PTEN bit is set. When the PTMR value matches the PTPER register, the PTMR register will be
reset on the following input clock edge and the PTEN bit will be cleared by the hardware to halt
the time base.
15.3.3 Up/Down Counting Modes
For the Continuous Up/Down Counting modes, the PWM time base will count upwards until the
value in the PTPER register is matched. The timer will begin counting downwards on the follow-
ing input clock edge and continue counting down until it reaches ‘0’. The PTDIR bit PTMR<15>
is read-only and indicates the counting direction. The PTDIR bit is set when the timer counts
downwards.
15.3.4 PWM Time Base Prescaler
The input clock to PTMR, (TCY) has prescaler options of 1:1, 1:4, 1:16 or 1:64 selected by
control bits PTCKPS<1:0> (PTCON<3:2>). The prescaler counter is cleared when any of the
following occurs:
• A write to the PTMR register
• A write to the PTCON register
• Any device reset
The PTMR register is not cleared when PTCON is written.
15.3.5 PWM Time Base Postscaler
The match output of PTMR can optionally be post-scaled through a 4-bit postscaler (which
gives a 1:1 to 1:16 scaling inclusive) to generate an interrupt. The postscaler is useful when the
PWM duty cycle does not need to be updated every PWM cycle.
The postscaler counter is cleared when any of the following occurs:
• A write to the PTMR register
• A write to the PTCON register
• Any device reset
The PTMR register is not cleared when PTCON is written.