dsPIC30F Family Reference Manual
DS70062C-page 15-18 © 2004 Microchip Technology Inc.
15.3.6 PWM Time Base Interrupts
The interrupt signals generated by the PWM time base depend on the mode selection bits,
PTMOD<1:0> (PTCON<1:0>), and the time base postscaler bits, PTOPS<3:0> (PTCON<7:4>).
• Free Running Mode
When the PWM time base is in the Free Running mode (PTMOD<1:0> = 00), an interrupt is
generated when the PTMR register is reset to ‘0’, due to a match with the PTPER register. The
postscaler selection bits may be used in this mode of the timer to reduce the frequency of the
interrupt events.
• Single Event Mode
When the PWM time base is in the Single Event mode (PTMOD<1:0> = 01), an interrupt is
generated when the PTMR register is reset to ‘0’ due to a match with the PTPER register. The
PTEN bit (PTCON<15>) is also cleared at this time to inhibit further PTMR increments. The
postscaler selection bits have no effect in this mode of the timer.
• Up/Down Counting Mode
In the Up/Down Counting mode (PTMOD<1:0> = 10), an interrupt event is generated each time
the value of the PTMR register becomes zero and the PWM time base begins to count upwards.
The postscaler selection bits may be used in this mode of the timer to reduce the frequency of
the interrupt events.
• Up/Down Counting Mode with Double Updates
In the Double Update mode (PTMOD<1:0> = 11), an interrupt event is generated each time the
PTMR register is equal to zero and each time a period match occurs. The postscaler selection
bits have no effect in this mode of the timer.
The Double Update mode allows the control loop bandwidth to be doubled because the PWM
duty cycles can be updated twice per period. Every rising and falling edge of the PWM signal
can be controlled using the double update mode.
15.3.7 PWM Period
The PTPER register sets the counting period for PTMR. The user must write a 15-bit value to
PTPER<14:0>. When the value in PTMR<14:0> matches the value in PTPER<14:0>, the time
base will either reset to ‘0’ or reverse the count direction on the next clock input edge. The action
taken depends on the operating mode of the time base.
The time base period is double buffered to allow on-the-fly period changes of the PWM signal
without glitches. The PTPER register serves as a buffer register to the actual time base period
register, which is not accessible by the user. The PTPER register contents are loaded into the
actual time base period register at the following times:
• Free Running and Single Event modes: when the PTMR register is reset to zero after a
match with the PTPER register.
• Up/Down Counting modes: When the PTMR register is zero.
The value held in the PTPER register is automatically loaded into the time base period register
when the PWM time base is disabled (PTEN = 0).
Figure 15-3 and Figure 15-4 indicate the times when the contents of the PTPER register are
loaded into the time base period register.
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