Microchip Technology dsPIC30F - DCI Operation

dsPIC30F Family Reference Manual
DS70069C-page 22-10 © 2004 Microchip Technology Inc.
The FS pulse has a minimum active time of one SCK period so the slave device can detect the
start of the data frame. The duty cycle of the FS pulse may vary depending on the specific pro-
tocol that is used to mark certain boundaries in the data frame. For example, the I
2
S protocol
uses a FS signal that has a 50% duty cycle. The I
2
S protocol is optimized for the transfer of two
data channels (left and right channel audio information). The edges of the FS signal mark the
boundaries of the left and right channel data words. The AC-Link protocol uses a FS signal that
is high for 16 SCK periods and low for 240 SCK periods. The edges of the AC-Link FS signal
mark the boundaries of control information and data in the frame.
22.4 DCI Operation
A simplified block diagram of the module is shown in Figure 22-4. The module consists of a
Transmit/Receive Shift register that is connected to a small range of memory buffers via a buffer
control unit. This arrangement allows the DCI to support various codec serial protocols. The DCI
Shift register is 16-bits wide. Data is transmitted and received by the DCI MSbit first.
Figure 22-4: DCI Module Block Diagram
Note: Refer to Section 26. “Appendix” of this manual for additional information on codec
communication protocols.
Clock Generator
CSCK
Frame
Generator
TCY
COFS
16-bit Data Bus
DCI Shift Register
CSDI
Buffer Control
WS<3:0>
COFSG<3:0>
COFSM<1:0>
COFSD
CSCKD
CSDO
0
15
Receive Registers w/
Buffer
Transmit Registers w/
Buffer
BCG<11:0>
Synchronization