© 2004 Microchip Technology Inc. DS70069C-page 22-9
Section 22. Data Converter Interface (DCI)
Data Converter
Interface (DCI)
22
All interfaces have a serial transfer clock, SCK. The SCK signal may be generated by any of the
connected devices or can be provided externally. In some systems, SCK is also referred to as
the bit clock. For codecs that offer high signal fidelity, it is common for the SCK signal to be
derived from the crystal oscillator on the codec device. The protocol defines the edge of SCK on
which data is sampled. The master device generates the FS signal with respect to SCK.
The period of the FS signal delineates one data frame. This period is the same as the data
sample period. The number of SCK cycles that occur during the data frame will depend on the
type of codec that is selected. The ratio of the SCK frequency to the system sample rate is
expressed as a ratio of n, where n is the number of SCK periods per data frame.
One advantage of using a framed interface protocol is that multiple data words can be transferred
during each sample period, or data frame. Each division of the data frame is referred to as a time
slot. The time slots can be used for multiple codec data channels and/or control information.
Furthermore, multiple devices can be multiplexed on the same serial data pins. Each slave
device is programmed to place its data on the serial data connection during the proper time slot.
The output of each slave device is tri-stated at all other times to permit other devices to use the
serial bus.
Some devices allow the FS signal to be daisy-chained via Frame Synchronization Output (FSO)
pins. A typical daisy-chained configuration is shown in Figure 22-1. When the transfer from the
first slave device has completed, a FS pulse is sent to the second device in the chain via its FSO
pin. This process continues until the last device in the chain has sent its data. The controller
(master) device should be programmed for a data frame size that accommodates all of the data
words that will be transferred.
The timing for a typical data transfer is shown in Figure 22-2. Most protocols begin the data
transfer one SCK cycle after the FS signal is detected. This example uses a 16 fs clock and
transfers four 4-bit data words per frame.
Figure 22-2: FRAMED DATA TRANSFER EXAMPLE
The timing for a typical data transfer with daisy-chained devices is shown in Figure 22-3. This
example uses a 16 fs SCK frequency and transfers two 8-bit data words per frame. After the FS
pulse is detected, the first device in the chain transfers the first 8-bit data word and generates the
FSO signal at the end of the transfer. The FSO signal begins the transfer of the second data word
from the second device in the chain.
Figure 22-3: DAISY-CHAINED DATA TRANSFER EXAMPLE
SCK
FS
Time Slot 0SDI or SDO Time Slot 1
Data Frame Period (1/fs)
FSO
SCK
FS
Time Slot 0 Time Slot 1
SDI or SDO
Time Slot 2
Time Slot 3
Data Frame Period (1/fs)
To Next Page
Loading...
