Microchip Technology dsPIC30F - Special Function Register Reset States

dsPIC30F Family Reference Manual
DS70055C-page 8-16 © 2004 Microchip Technology Inc.
The Reset time line shown in Figure 8-8 shows an example where an EC without PLL, or RC
system clock source is selected and the PWRT is disabled. Note that this configuration provides
minimal Reset delays. The POR delay is the only delay time that occurs before device operation
begins. No FSCM delay will occur if the FSCM is enabled, because the system clock source is
not derived from a crystal oscillator or the PLL.
Figure 8-8: Device Reset Delay, EC or RC Clock, PWRT Disabled
8.11 Special Function Register Reset States
Most of the special function registers (SFRs) associated with the dsPIC30F CPU and peripherals
are reset to a particular value at a device Reset. The SFRs are grouped by their peripheral or
CPU function and their Reset values are specified in each section of this manual.
The Reset value for each SFR does not depend on the type of Reset, with the exception of two
registers. The Reset value for the Reset Control register, RCON, will depend on the type of
device Reset. The Reset value for the Oscillator Control register, OSCCON, will depend on the
type of Reset and the programmed values of the oscillator configuration bits in the FOSC Device
Configuration register (see Table 8-1).
POR Circuit Threshold Voltage
SYSRST
Internal Power-on Reset Pulse
TPOR
VDD
Oscillator released to system.
POR
System Reset released.
Note 1: Delay times shown are not drawn to scale.
2: If enabled, FSCM will begin to monitor system clock at expiration of TPOR.
FSCM
OSC Delay