dsPIC30F Family Reference Manual
DS70055C-page 8-2 © 2004 Microchip Technology Inc.
8.1 Introduction
The Reset module combines all Reset sources and controls the device Master Reset Signal,
SYSRST
. The following is a list of device Reset sources:
• POR: Power-on Reset
• EXTR: Pin Reset (MCLR
)
•SWR: RESET Instruction
• WDTR: Watchdog Timer Reset
• BOR: Brown-out Reset
• TRAPR: Trap Conflict Reset
• IOPR: Illegal Opcode Reset
• UWR: Uninitialized W Register Reset
A simplified block diagram of the Reset module is shown in Figure 8-1. Any active source of
Reset will make the SYSRST
signal active. Many registers associated with the CPU and periph-
erals are forced to a known “Reset state”. Most registers are unaffected by a Reset; their status
is unknown on POR and unchanged by all other Resets.
All types of device Reset will set a corresponding status bit in the RCON register to indicate the
type of Reset (see Register 8-1). A POR will clear all bits except for the POR and BOR bits
(RCON<2:1>), which are set. The user may set or clear any bit at any time during code execution.
The RCON bits only serve as status bits. Setting a particular Reset status bit in software will not
cause a device Reset to occur.
The RCON register also has other bits associated with the Low Voltage Detect module,
Watchdog Timer, and device power saving states. The function of these bits is discussed in other
sections of this manual.
Figure 8-1: Reset System Block Diagram
Note: Refer to the specific peripheral or CPU section of this manual for register Reset
states.
MCLR
VDD
VDD Rise
Detect
POR
Sleep or Idle
Brown-out
Reset
BOREN
RESET
Instruction
WDT
Module
Glitch Filter
BOR
Trap Conflict
Illegal Opcode
Uninitialized W Register
SYSRST
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