© 2004 Microchip Technology Inc. DS70055C-page 8-3
Section 8. Reset
Reset
8
Register 8-1: RCON: Reset Control Register
Upper Byte:
R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1
TRAPR IOPUWR BGST LVDEN LVDL<3:0>
bit 15 bit 8
Lower Byte:
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1
EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR
bit 7 bit 0
bit 15 TRAPR: Trap Reset Flag bit
1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1 = An illegal opcode detection, an illegal Address mode, or uninitialized W register used as an address
pointer caused a Reset
0 = An illegal opcode or uninitialized W Reset has not occurred
bit 13 BGST: Bandgap Stable bit
1 = The bandgap has stabilized
0 = Bandgap is not stable and LVD interrupts should be disabled
bit 12 LVDEN: Low Voltage Detect Power Enable bit
1 = Enables LVD, powers up LVD circuit
0 = Disables LVD, powers down LVD circuit
bit 11-8 LVDL<3:0>: Low Voltage Detection Limit bits
Refer to Section 9. “Low Voltage Detect (LVD)” for further details.
bit 7 EXTR: External Reset (MCLR
) Pin bit
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
bit 6 SWR: Software RESET (Instruction) Flag bit
1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed
bit 5 SWDTEN: Software Enable/Disable of WDT bit
1 = WDT is turned on
0 = WDT is turned off
Note: If FWDTEN fuse bit is ‘1’ (unprogrammed), the WDT is ALWAYS ENABLED, regardless of the
SWDTEN bit setting.
bit 4 WDTO: Watchdog Timer Time-out Flag bit
1 = WDT Time-out has occurred
0 = WDT Time-out has not occurred
bit 3 SLEEP: Wake From Sleep Flag bit
1 = Device has been in Sleep mode
0 = Device has not been in Sleep mode
bit 2 IDLE: Wake-up From Idle Flag bit
1 = Device was in Idle mode
0 = Device was not in Idle mode
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