© 2004 Microchip Technology Inc. DS70069C-page 22-17
Section 22. Data Converter Interface (DCI)
Data Converter
Interface (DCI)
22
22.5 Using the DCI Module
This section explains how to configure and use the DCI with specific kinds of data converters.
22.5.1 How to Transmit and Receive Data Using the DCI Buffers, Status Bits and Interrupts
The DCI can buffer up to four data words between CPU interrupts depending on the setting of
the BLEN control bits. The buffered data can be transmitted and received in a single data frame,
or across multiple data frames, depending on the TSCON and RSCON register settings. For
example, assume BLEN<1:0> = 00b ( buffer one data word per interrupt) and TSCON = RSCON
= 0x0001. This particular configuration represents the most basic setup and would cause the
DCI to transmit/receive one data word at the beginning of every data frame. The CPU would be
interrupted after every data word transmitted/received since BLEN<1:0> = 00b.
For a second configuration example, assume BLEN<1:0> = 11b (buffer four data words per
interrupt) and TSCON = RSCON = 0x0001. This configuration would cause the DCI to
transmit/receive one data word at the beginning of every data frame, but a CPU interrupt would
be generated after four data words were transmitted/received. This configuration would be useful
for block processing, where multiple data samples are processed at once.
For a third configuration example, assume BLEN<1:0> = 11b (buffer four data words per
interrupt) and TSCON = RSCON = 0x000F. This configuration would cause the DCI to
transmit/receive four data words at the beginning of every data frame. A CPU interrupt would be
generated every data frame in this case because the DCI was setup to buffer four data words in
a data frame. This configuration represents a typical multi-channel buffering setup.
The DCI can also be configured to buffer more than four data words per frame. For example,
assume BLEN<1:0> = 11b (buffer four data words per interrupt) and TSCON = RSCON =
0x00FF. In this configuration, the DCI will transmit/receive 8 data words per data frame. An
interrupt will be generated twice per data frame. To determine which portion of the data is in the
Transmit/Receive registers at each interrupt, the user will need to check the SLOT status bits
(DCISTAT <11:7>) in the Interrupt Service Routine to determine the current data frame position.
The Transmit and Receive registers are double-buffered, so the DCI module can work on one set
of Transmit and Receive data while the user software is manipulating the other set of data.
Because of the double-buffers, it will take three interrupt periods to receive the data, process that
data, and transmit the processed data. For each DCI interrupt, the CPU will process a data word
that was received during a prior interrupt period and generate a data word that will be transmitted
during the next interrupt period. The buffering and data processing time of the dsPIC device will
insert a two-interrupt period delay into the processed data. This data delay is negligible, in most
cases.
The DCI status flags and CPU interrupt indicate that a buffer transfer has taken place and that it
is time for the CPU to process more data. In a typical application, the following steps will occur
each time the DCI data is processed:
1. The RXBUF registers are read by the user software. The RFUL status bit (DCISTAT<2>)
will have been set by the module to indicate the Receive registers contain new data. The
RFUL bit is cleared automatically after all the active Receive registers have been read.
2. The user software will process the received data.
3. The processed data is written to the TXBUF registers. The TMPTY status bit
(DCISTAT<0>) will have been previously set to indicate that the Transmit registers are
ready for more data to be written.
For applications that are configured to Transmit and Receive data (TSCON and RSCON are
non-zero), the RFUL and TMPTY status bits can be polled in user software to determine when a
DCI buffer transfer takes place. If the DCI is only used to transmit data (RSCON = 0), then the
TMPTY bit can be polled to indicate a buffer transfer. If the DCI is configured to only receive data
(TSCON = 0), then the RFUL bit can be polled to indicate a buffer transfer.
The DCIIF status bit (IFS2<9>) is set each time a DCI buffer transfer takes place and generates
a CPU interrupt, if enabled. The DCIIF status bit is generated by the logical ORing of the RFUL
and TMPTY status bits.
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