© 2004 Microchip Technology Inc. DS70074C-page 26-25
Section 26. Appendix
Appendix
26
APPENDIX C: CODEC PROTOCOL OVERVIEW
This appendix summarizes audio coder/decoder (codec) protocols for Inter-IC Sound (I
2
S) and
AC-Link Compliant mode interfaces. Many codecs intended for use in audio applications
support sampling rates between 8 kHz and 48 kHz and typically use one of the interface
protocols previously mentioned. The Data Converter Interface (DCI) module automatically
handles the interface timing associated with these codecs. No overhead from the CPU is
required until the requested amount of data has been transmitted and/or received by the DCI.
Up to four data words may be transferred between CPU interrupts.
C.1 I
2
S Protocol Description
Inter-IC Sound (I
2
S) is a simple, three-wire bus interface used for the transfer of digital audio
data between the following devices:
• DSP processors
• A/D and D/A converters
• Digital input/output interfaces
This Appendix information is intended to supplement the I
2
S Protocol Specification
®
, which is
published by Philips, Inc.
The I
2
S bus is a time division multiplexed and transfers two channels of data. These two data
channels are typically the left and right channels of a digital audio stream.
The I
2
S bus has the following connection pins:
• SCK: The I
2
S serial clock line
• SDx: The I
2
S serial data line (input or output)
• WS: The I
2
S word select line
A timing diagram for a data transfer is shown in Figure C-2. Serial data is transmitted on the I
2
S
bus in two’s complement format with the MSb transmitted first. The MSb must be transferred
first because the protocol allows different transmitter and receiver data word lengths. If a
receiver is sent more bits than in can accept for a data word, the LSbits are ignored. If a receiver
is sent fewer bits than its native word length, it must set the remaining LSbits to zero internally.
The WS line indicates the data channel that is being transmitted. The following standard is
used:
•WS = 0: Channel 1 or left audio channel
•WS = 1: Channel 2 or right audio channel
The WS line is sampled by the receiver on the rising edge of SCK and the MSb of the next data
word is transmitted one SCK period after WS changes. The one period delay after WS changes
provides the receiver time to store the previously transmitted word and prepare for the next
word. Serial data sent by the transmitter is placed on the bus on the falling edge of SCK and is
latched by the receiver on the rising edge of SCK.
Any device may act as the system master in an I
2
S system. The system master generates the
SCK and WS signals. Typically, the transmitter is the system master, but the receiver or a third
device may perform this function. Figure C-1 shows possible I
2
S bus configurations. Although it
is not indicated in Figure C-1, the two connected devices may have both a data transmit and a
data receive connection.
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