dsPIC30F Family Reference Manual
DS70074C-page 26-26 © 2004 Microchip Technology Inc.
Figure C-1: I
2
S Bus Connections
Figure C-2: I
2
S Interface Timing Diagram
C.2 AC ‘97 Protocol
The Audio Codec ‘97 (AC ‘97) specification defines a standard architecture and digital interface
protocol for audio codecs used in PC platforms. The digital interface protocol for an AC ‘97
compliant codec is called AC-Link and is the focus of this discussion. The specific requirements
and features of the AC ‘97 controller device are not described here.
This Appendix information is intended to supplement the AC ‘97 Component Specification
document, which is published by Intel, Corp.
C.3 AC-Link Signal Descriptions
All AC-Link signals are derived from the AC ‘97 master clock source. The recommended clock
source is a 24.576 MHz crystal connected to the AC ‘97 codec to minimize clock jitter. The
24.576 MHz clock may also be provided by the AC ‘97 controller or by an external source.
All AC-Link signal names are referenced to the AC ‘97 controller, not the AC ‘97 codec. The
controller is the device that generates the SYNC signal to initiate data transfers. Each signal is
described in subsequent sections.
SCK
WS
SD
SCK
WS
SD
I
2
S Receiver
SCK
WS
SD
Transmitter master
Receiver master
Separate controller as master
I
2
S Transmitter
I
2
S Controller
I
2
S Transmitter I
2
S Receiver
I
2
S ReceiverI
2
S Transmitter
Note: A 5 bit transfer is shown here for illustration purposes. The I
2
S protocol does
not specify word length – this is system dependent.
MSB LSB MSB LSB
SCK
SD
WS
To Next Page
Loading...
