© 2004 Microchip Technology Inc. DS70074C-page 26-27
Section 26. Appendix
Appendix
26
C.3.1 Bit Clock (BIT_CLK)
A 12.288 MHz BIT_CLK signal is provided by the master AC ’97 codec in a system. The
BIT_CLK signal is an input to the AC ‘97 controller and up to three slave AC ‘97 codec devices
in the system. All data on the AC-Link transitions on the rising edge of BIT_CLK and is sampled
by the receiving device on the falling edge of BIT_CLK.
C.3.2 Serial Data Output (SDO)
SDO is a time division multiplexed data stream sent to the AC ‘97 codec
C.3.3 Serial Data Input (SDI)
SDI is the time division multiplexed data stream from the AC ‘97 codec.
C.3.4 SYNC
SYNC is a 48 kHz fixed rate sample synchronization signal that is supplied from the AC ‘97
controller to the AC ‘97 codec. The SYNC signal is derived by dividing the BIT_CLK signal by
256. The SYNC signal is high for 16 BIT_CLK periods and is low for 240 BIT_CLK periods. The
SYNC signal only changes on the rising edge of BIT_CLK and its period defines the boundaries
of one audio data frame.
C.3.5 Reset
The RESET
signal is an input to each AC ‘97 codec in the system and resets the codec
hardware.
C.4 AC-Link Protocol
C.4.1 AC-Link Serial Interface Protocol
The AC-Link serial data stream uses a time division multiplexed (TDM) scheme with a 256-bit
data frame. Each data frame is subdivided into 13 time slots, numbered Slot #0 – Slot #12. Slot
#0 is a special time slot that contains 16 bits. The remaining 12 slots are 20-bits wide.
An example of an AC-Link frame is shown in Figure C-4. The frame begins with a rising edge of
the SYNC signal which is coincident with the rising edge of BIT_CLK. The AC ‘97 codec
samples the assertion of SYNC on the falling edge of BIT_CLK that immediately follows. This
falling edge marks the time when both the codec and controller are aware of the start of a new
frame. On the next rising edge of BIT_CLK, the codec asserts the MSb of SDATA_IN and the
codec asserts the first edge of SDATA_OUT. This sequence ensures that data transitions and
subsequent sample points for both incoming and outgoing data streams are time aligned.
Slot #0, Slot #1 and Slot #2 have special use for status and control in the AC-Link protocol. The
remaining time slots are assigned to certain types of digital audio data. The data assignment for
Slot #3 – Slot #12 is dependent on the AC ‘97 codec that is selected, so the slot usage is
summarized briefly here. For more details on slot usage, refer to the AC ‘97 Component
Specification.
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