Microchip Technology dsPIC30F - Design Tips

dsPIC30F Family Reference Manual
DS70068C-page 21-50 © 2004 Microchip Technology Inc.
21.11 Design Tips
Question 1: I’m operating as a bus master and transmitting data, however, slave and
receive interrupts are also occurring.
Answer: The master and slave circuits are independent. The slave module will receive events
from the bus sent by the master.
Question 2: I’m operating as a slave and I write data to the I2CTRN register, but the data
did not transmit.
Answer: The slave enters an automatic wait when preparing to transmit. Ensure that you set
the SCLREL bit to release the I
2
C clock.
Question 3: How do I tell what state the master module is in?
Answer: Looking at the condition of SEN, RSEN, PEN, RCEN, ACKEN and TRSTAT bits will
indicate the state of the master module. If all bits are ‘0’, the module is Idle.
Question 4: Operating as a slave, I receive a byte while STREN = 0. What should the
software do if it cannot process the byte before the next one is received?
Answer: Because STREN was ‘0’, the module did not generate an automatic WAIT on the
received byte. However, the software may, at any time during the message, set STREN then
clear SCLREL. This will cause a WAIT on the next opportunity to synchronize the SCL clock.
Question 5: My I
2
C system is a multi-master system. When I attempt to send a message,
it is being corrupted.
Answer: In a multi-master system, other masters may cause bus collisions. In the Interrupt
Service Routine for the master, check the BCL bit to ensure that the operation completed
without a collision. If a collision is detected, the message must be resent from the beginning.
Question 6: My I
2
C system is a multi-master system. How can I tell when it is OK to
begin a message?
Answer: Look at the S and P bits. If S = 0 and P = 0 the bus is Idle. If S = 0 and P = 1, the bus
is Idle.
Question 7: I tried to send a Start condition on the bus, then transmit a byte by writing
to the I2CTRN register. The byte did not get transmitted. Why?
Answer: You must wait for each event on the I
2
C bus to complete before starting the next one.
In this case, you should poll the SEN bit to determine when the Start event completed, or wait for
the master I
2
C interrupt before data is written to I2CTRN.