dsPIC30F Family Reference Manual
DS70058C-page 11-6 © 2004 Microchip Technology Inc.
11.5.1 CN Control Registers
There are four control registers associated with the CN module. The CNEN1 and CNEN2
registers contain the CNxIE control bits, where ‘x’ denotes the number of the CN input pin. The
CNxIE bit must be set for a CN input pin to interrupt the CPU.
The CNPU1 and CNPU2 registers contain the CNxPUE control bits. Each CN pin has a weak
pull-up device connected to the pin, which can be enabled or disabled using the CNxPUE control
bits. The weak pull-up devices act as a current source that is connected to the pin and eliminate
the need for external resistors when push button or keypad devices are connected. Refer to the
“Electrical Specifications” section of the device data sheet for CN pull-up device current
specifications.
11.5.2 CN Configuration and Operation
The CN pins are configured as follows:
1. Ensure that the CN pin is configured as a digital input by setting the associated bit in the
TRISx register.
2. Enable interrupts for the selected CN pins by setting the appropriate bits in the CNEN1
and CNEN2 registers.
3. Turn on the weak pull-up devices (if desired) for the selected CN pins by setting the
appropriate bits in the CNPU1 and CNPU2 registers.
4. Clear the CNIF (IFS0<15>) interrupt flag.
5. Select the desired interrupt priority for CN interrupts using the CNIP<2:0> control bits
(IPC3<14:12>).
6. Enable CN interrupts using the CNIE (IEC0<15>) control bit.
When a CN interrupt occurs, the user should read the PORT register associated with the CN
pin(s). This will clear the mismatch condition and setup the CN logic to detect the next pin
change. The current PORT value can be compared to the PORT read value obtained at the last
CN interrupt to determine the pin that changed.
The CN pins have a minimum input pulse width specification. Refer to the “Electrical
Specifications” section of the device data sheet for further details.
11.6 CN Operation in Sleep and Idle Modes
The CN module continues to operate during Sleep or Idle modes. If one of the enabled CN pins
changes states, the CNIF (IFS0<15>) status bit will be set. If the CNIE bit (IEC0<15>) is set, the
device will wake from Sleep or Idle mode and resume operation.
If the assigned priority level of the CN interrupt is equal to or less than the current CPU priority
level, device execution will continue from the instruction immediately following the SLEEP or
IDLE instruction.
If the assigned priority level of the CN interrupt is greater than the current CPU priority level,
device execution will continue from the CN interrupt vector address.
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