dsPIC30F Family Reference Manual
DS70065C-page 18-12 © 2004 Microchip Technology Inc.
18.7 Selecting the A/D Conversion Clock
The A/D converter has a maximum rate at which conversions may be completed. An analog
module clock, T
AD, controls the conversion timing. The A/D conversion requires 14 clock periods
(14 T
AD). The A/D clock is derived from the device instruction clock.
The period of the A/D conversion clock is software selected using a six-bit counter. There are 64
possible options for T
AD, specified by the ADCS<5:0> bits (ADCON3<5:0>). Equation 18-1 gives
the T
AD value as a function of the ADCS control bits and the device instruction cycle clock period,
T
CY.
Equation 18-1: A/D Conversion Clock Period
For correct A/D conversions, the A/D conversion clock (T
AD) must be selected to ensure a
minimum T
AD time of 667 nsec (for VDD = 5V).
The A/D converter has a dedicated internal RC clock source that can be used to perform
conversions. The internal RC clock source should be used when A/D conversions are performed
while the dsPIC30F is in Sleep mode. The internal RC oscillator is selected by setting the ADRC
bit (ADCON3<7>). When the ADRC bit is set, the ADCS<5:0> bits have no effect on the A/D
operation.
18.8 Selecting Analog Inputs for Sampling
The Sample-and-Hold Amplifier has analog multiplexers (see Figure 18-1) on both its
non-inverting and inverting inputs, to select which analog input(s) are sampled. Once the
sample/convert sequence is specified, the ADCHS bits determine which analog inputs are
selected for each sample.
Additionally, the selected inputs may vary on an alternating sample basis, or may vary on a
repeated sequence of samples.
18.8.1 Configuring Analog Port Pins
The ADPCFG register specifies the input condition of device pins used as analog inputs.
A pin is configured as analog input when the corresponding PCFGn bit (ADPCFG<n>) is clear.
The ADPCFG register is clear at Reset, causing the A/D input pins to be configured for analog
input by default at Reset.
When configured for analog input, the associated port I/O digital input buffer is disabled so it does
not consume current.
The ADPCFG register and the TRISB register control the operation of the A/D port pins.
The port pins that are desired as analog inputs must have their corresponding TRIS bit set,
specifying port input. If the I/O pin associated with an A/D input is configured as an output, TRIS
bit is cleared, the pin is in Analog mode (ADPCFG<n> = 0) and the port digital output level (V
OH
or VOL) will be converted. After a device Reset, all TRIS bits are set.
A pin is configured as digital I/O when the corresponding PCFGn bit (ADPCFG<n>) is set. In this
configuration, the input to the analog multiplexer is connected to AV
SS.
T
AD =
T
CY (ADCS + 1)
2
ADCS =
2T
AD
TCY
– 1
Note: Different devices will have different numbers of analog inputs. Verify the analog
input availability against the device data sheet.
Note 1: When reading a port register, any pin configured as an analog input reads as a ‘0’.
2: Analog levels on any pin that is defined as a digital input (including the AN15:AN0
pins) may cause the input buffer to consume current that is out of the device’s
specification.
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