Microchip Technology dsPIC30F - Communicating as a Master in a Multi-Master Environment

© 2004 Microchip Technology Inc. DS70068C-page 21-29
Section 21. Inter-Integrated Circuit (I
2
C)
Inter-Integrated
Circuit (I
2
C)
21
21.6 Communicating as a Master in a Multi-Master Environment
The I2C protocol allows for more than one master to be attached to a system bus. Remember-
ing that a master can initiate message transactions and generate clocks for the bus, the
protocol has methods to account for situations where more than one master is attempting to
control the bus. Clock synchronization ensures that multiple nodes can synchronize their SCL
clocks to result in one common clock on the SCL line. Bus arbitration ensures that if more than
one node attempts a message transaction, one and only one node will be successful in
completing the message. The other nodes will lose bus arbitration and be left with a bus
collision.
21.6.1 Multi-Master Operation
The master module has no special settings to enable multi-master operation. The module
performs clock synchronization and bus arbitration at all times. If the module is used in a single
master environment, clock synchronization will only occur between the master and slaves and
bus arbitration will not occur.
21.6.2 Master Clock Synchronization
In a multi-master system, different masters may have different baud rates. Clock synchronization
will ensure that when these masters are attempting to arbitrate the bus, their clocks will be
coordinated.
Clock synchronization occurs when the master de-asserts the SCL pin (SCL intended to float
high). When the SCL pin is released, the baud rate generator (BRG) is suspended from counting
until the SCL pin is actually sampled high. When the SCL pin is sampled high, the baud rate
generator is reloaded with the contents of I2CBRG<8:0> and begins counting. This ensures that
the SCL high time will always be at least one BRG rollover count in the event that the clock is
held low by an external device, as shown in Figure 21-19.
Figure 21-19: Baud Rate Generator Timing with Clock Synchronization
SCL (Slave)
- The baud counter decrements twice per TCY. On rollover, the master SCL will transition.
1
1
000
003
001002003000
SCL (Master)
001002003000
Baud Counter
SDA (Master)
3 4 6
- The slave has pulled SCL low to initiate a wait.
2
- At what would be the master baud counter rollover, detecting SCL low holds counter.
3
- Logic samples SCL once per T
CY. Logic detects SCL high.
4
2
- The baud counter rollover occurs on next cycle.
5
5
- On next rollover, the master SCL will transition.
6
T
BRG
TBRG
TCY