dsPIC30F Family Reference Manual
DS70068C-page 21-30 © 2004 Microchip Technology Inc.
21.6.3 Bus Arbitration and Bus Collision
Bus arbitration supports multi-master system operation.
The wired-and nature of the SDA line permits arbitration. Arbitration takes place when the first
master outputs a ‘1’ on SDA by letting SDA float high and, simultaneously, the second master
outputs a ‘0’ on SDA by pulling SDA low. The SDA signal will go low. In this case, the second
master has won bus arbitration. The first master has lost bus arbitration and thus has a bus
collision.
For the first master, the expected data on SDA is a ‘1’ yet the data sampled on SDA is a ‘0’. This
is the definition of a bus collision.
The first master will set the bus collision bit, BCL (I2CSTAT<10>), and generate a master
interrupt. The master module will reset the I
2
C port to its Idle state.
In multi-master operation, the SDA line must be monitored for arbitration to see if the signal
level is the expected output level. This check is performed by the master module, with the result
placed in the BCL bit.
The states where arbitration can be lost are:
• A Start condition
• A Repeated Start condition
• Address, Data or Acknowledge bit
• A Stop condition
21.6.4 Detecting Bus Collisions and Resending Messages
When a bus collision occurs, the module sets the BCL bit and generates a master interrupt. If
bus collision occurs during a byte transmission, the transmission is halted, the TBF flag is
cleared and the SDA and SCL pins are de-asserted. If bus collision occurs during a Start,
Repeated Start, Stop or Acknowledge condition, the condition is aborted, the respective control
bits in the I2CCON register are cleared and the SDA and SCL lines are de-asserted.
The software is expecting an interrupt at the completion of the master event. The software can
check the BCL bit to determine if the master event completed successfully or if a collision
occurred. If a collision occurs, the software must abort sending the rest of the pending message
and prepare to resend the entire message sequence beginning with Start condition, after the
bus returns to an Idle state. The software can monitor the S and P bits to wait for an Idle bus.
When the software services the master Interrupt Service Routine and the I
2
C bus is free, the
software can resume communication by asserting a Start condition.
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