© 2004 Microchip Technology Inc. DS70068C-page 21-13
Section 21. Inter-Integrated Circuit (I
2
C)
Inter-Integrated
Circuit (I
2
C)
21
21.4 Enabling I
2
C Operation
The module is enabled by setting the I2CEN (I2CCON<15>) bit.
The I
2
C module fully implements all master and slave functions. When the module is enabled,
the master and slave functions are active simultaneously and will respond according to the
software or the bus events.
When initially enabled, the module will release SDA and SCL pins, putting the bus into the Idle
state. The master functions will remain in the Idle state unless software sets a control bit to
initiate a master event. The slave functions will begin to monitor the bus. If the slave logic
detects a Start event and a valid address on the bus, the slave logic will begin a slave
transaction.
21.4.1 Enabling I
2
C I/O
Two pins are used for bus operation. These are the SCL pin, which is the clock, and the SDA
pin, which is the data. When the module is enabled, assuming no other module with higher
priority has control, the module will assume control of the SDA and SCL pins. The module
software need not be concerned with the state of the port I/O of the pins, the module overrides
the port state and direction. At initialization, the pins are tri-state (released).
21.4.2 I
2
C Interrupts
The I
2
C module generates two interrupts. One interrupt is assigned to master events and the
other interrupt is assigned to slave events. These interrupts will set a corresponding interrupt
flag bit and will interrupt the software process if the corresponding interrupt enable bit is set and
the corresponding interrupt priority is high enough.
The master interrupt is called MI2CIF and is activated on completion of a master message
event.
The following events generate the MI2CIF interrupt.
• Start condition
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
• Detection of a bus collision event
The slave interrupt is called SI2CIF and is activated on detection of a message directed to the
slave.
• Detection of a valid device address (including general call)
• Request to transmit data
• Reception of data