Microchip Technology dsPIC30F - Page 528

dsPIC30F Family Reference Manual
DS70068C-page 21-14 © 2004 Microchip Technology Inc.
21.4.3 Setting Baud Rate when Operating as a Bus Master
When operating as an I
2
C master, the module must generate the system SCL clock. Generally,
I
2
C system clocks are specified to be either 100 kHz, 400 kHz or 1 MHz. The system clock rate
is specified as the minimum SCL low time plus the minimum SCL high time. In most cases, that
is defined by 2 T
BRG intervals.
The reload value for the baud rate generator is the I2CBRG register, as shown in Figure 21-6.
When the baud rate generator is loaded with this value, the generator counts down to ‘0’ and
stops until another reload has taken place. The generator count is decremented twice per
instruction cycle (T
CY). The baud rate generator is reloaded automatically on baud rate restart.
For example, if clock synchronization is taking place, the baud rate generator will be reloaded
when the SCL pin is sampled high.
To compute the baud rate generator reload value, use the following equation.
Equation 21-1:
Table 21-1: I
2
C Clock Rates
Figure 21-6: Baud Rate Generator Block Diagram
Note: I2CBRG value of 0x0 is not supported.
I2CBRG =
F
CY FCY
FSCL 1,111,111
– 1
–
()
Required
System
F
SCL
FCY
I2CBRG
Decimal
I2CBRG
HEX
Actual
F
SCL
100 kHz 40 MHz 399 0x18F 100 kHz
100 kHz 30 MHz 299 0x12B 100 kHz
100 kHz 20 MHz 199 0x0C7 100 kHz
400 kHz 10 MHz 24 0x018 400 kHz
400 kHz 4 MHz 9 0x009 400 kHz
400 kHz 1 MHz 2 0x002 333 kHz**
1 MHz* 2 MHz 1 0x001 1 MHz*
1 MHz 1 MHz 0 0x000
(invalid)
1 MHz
*F
CY = 2 MHz is the minimum input clock frequency to have FSCL = 1 MHz.
** This is closest value to 400 kHz for this value of F
CY.
Down Counter
CLK
2 T
CY
I2CBRG<8:0>
SCL
Reload
Control
Reload