dsPIC30F Family Reference Manual
DS70074C-page 26-2 © 2004 Microchip Technology Inc.
APPENDIX A: I
2
C OVERVIEW
This appendix provides an overview of the Inter-Integrated Circuit (I
2
C™) bus, with Subsection
A.2 “Addressing I
2
C Devices” discussing the operation of the SSP modules in I
2
C mode.
The I
2
C bus is a two-wire serial interface. The original specification, or standard mode, is for
data transfers of up to 100 Kbps. An enhanced specification, or fast mode (400 Kbps), is
supported. Standard and Fast mode devices will operate when attached to the same bus, if the
bus operates at the speed of the slower device.
The I
2
C interface employs a comprehensive protocol to ensure reliable transmission and
reception of data. When transmitting data, one device is the “master”, which initiates transfer on
the bus and generates the clock signals to permit that transfer, while the other device(s) acts as
the “slave.” All portions of the slave protocol are implemented in the SSP module’s hardware,
except general call support, while portions of the master protocol need to be addressed in the
PIC16CXX software. The MSSP module supports the full implementation of the I
2
C master
protocol, the general call address and data transfers up to 1 Mbps. The 1 Mbps data transfers
are supported by some of Microchip’s Serial EEPROMs. Table A-1 defines some of the I
2
C bus
terminology.
In the I
2
C interface protocol, each device has an address. When a master wishes to initiate a
data transfer, it first transmits the address of the device that it wishes to “talk” to. All devices
“listen” to see if this is their address. Within this address, a bit specifies if the master wishes to
read-from/write-to the slave device. The master and slave are always in opposite modes
(transmitter/receiver) of operation during a data transfer. That is, they can be thought of as
operating in either of these two relations:
• Master-transmitter and Slave-receiver
• Slave-transmitter and Master-receiver
In both cases, the master generates the clock signal.
The output stages of the clock (SCL) and data (SDA) lines must have an open-drain or
open-collector in order to perform the wired-AND function of the bus. External pull-up resistors
are used to ensure a high level when no device is pulling the line down. The number of devices
that may be attached to the I
2
C bus is limited only by the maximum bus loading specification of
400 pF and addressing capability.
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