© 2004 Microchip Technology Inc. DS70068C-page 21-31
Section 21. Inter-Integrated Circuit (I
2
C)
Inter-Integrated
Circuit (I
2
C)
21
21.6.5 Bus Collision During a Start Condition
Before issuing a Start command, the software should verify an Idle state of the bus using the S
and P status bits. Two masters may attempt to initiate a message at a similar point in time.
Typically, the masters will synchronize clocks and continue arbitration into the message until
one loses arbitration. However, certain conditions can cause a bus collision to occur during a
Start. In this case, the master that loses arbitration during the Start bit generates a bus collision
interrupt.
21.6.6 Bus Collision During a Repeated Start Condition
Should two masters not collide throughout an address byte, a bus collision may occur when one
master attempts to assert a Repeated Start while another transmits data. In this case, the
master generating the Repeated Start will lose arbitration and generate a bus collision interrupt.
21.6.7 Bus Collision During Message Bit Transmission
The most typical case of data collision occurs while the master is attempting to transmit the
device address byte, a data byte or an Acknowledge bit.
If the software is properly checking the bus state, it is unlikely that a bus collision will occur on a
Start condition. However, because another master can at a very similar time, check the bus and
initiate its own Start condition, it is likely that SDA arbitration will occur and synchronize the
starts of two masters. In this condition, both masters will begin and continue to transmit their
messages until one master loses arbitration on a message bit. Remember that SCL clock
synchronization will keep the two masters synchronized until one loses arbitration.
Figure 21-20 shows an example of message bit arbitration.
Figure 21-20: Bus Collision During Message Bit Transmission
21.6.8 Bus Collision During a Stop Condition
If the master software loses track of the state of the I
2
C bus, there are conditions which cause a
bus collision during a Stop condition. In this case, the master generating the Stop condition will
lose arbitration and generate a bus collision interrupt.
SCL (Master)
SDA (Master)
TBF
T
BRG
1 2 3
- Master transmits bit value of ‘1’ in next SCL clock.
1
TBRG
Module releases SDA.
- Another master on bus transmits bit value of ‘0’
2
in next SCL clock. Another master pulls SDA low.
- Baud generator times out. Module attempts to verify
3
I
2
C Bus State
BCL
(D)
SCL (Bus)
SDA (Bus)
SDA high. Bus collision detected.
Module releases SDA, SCL. Module sets BCL bit and
clears TBF bit. Master generates interrupt.
(D)
(Q)
(Q)
(Q)
MI2CIF Interrupt
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