dsPIC30F Family Reference Manual
DS70069C-page 22-16 © 2004 Microchip Technology Inc.
22.4.14 Transmit Status Bits
There are two transmit status bits, TMPTY and TUNF.
The transmit status bits only indicate status for register locations that are used by the module. If
the buffer length is set to less than four words, for example, the unused register locations will not
affect the transmit status bits.
The TMPTY bit (DCISTAT<0>) is read only and is set when the contents of the active TXBUF
registers are transferred to the Transmit Buffer registers. The TMPTY bit may be polled in
software to determine when the Transmit registers may be written. The TMPTY bit is cleared
automatically by the hardware when a write to any of the TXBUF registers in use occurs.
The TUNF bit (DCISTAT<1>) is read only and indicates that a transmit underflow has occurred
for at least one of the Transmit registers that is in use. The TUNF bit is set when the TXBUF
register contents are transferred to the transmit buffer memory and the user did not write all of
the TXBUF registers in use since the last buffer transfer. The TUNF status bit is cleared
automatically when the TXBUF register that underflowed is written by the user software.
22.4.15 SLOT Status Bits
The SLOT<3:0> status bits (DCISTAT<11:7>) indicate the current active time slot in the data
frame and are useful when more than four words per data frame need to be transferred. The user
may poll these status bits in software when a DCI interrupt occurs to determine what time slot
data was last received and which time slot data should be loaded into the TXBUF registers.
22.4.16 Digital Loopback Mode
Digital Loopback mode is enabled by setting the DLOOP control bit (DCICON1<11>). When the
DLOOP bit is set, the module internally connects the CSDO signal to CSDI. The actual data input
on the CSDI pin will be ignored in Digital Loopback mode.
22.4.17 Underflow Mode Control Bit
When a transmit underflow occurs, one of two actions may occur depending on the state of the
UNFM control bit (DCICON1<7>). If the UNFM bit is cleared (default), the module will transmit
‘0’s on the CSDO pin during the active time slot for the buffer location. In this Operating mode,
the codec device attached to the DCI module will simply be fed digital ‘silence’. If the UNFM
control bit is set, the module will transmit the last data written to the buffer location. This
Operating mode permits the user to send a continuous data value to the codec device without
consuming software overhead.
22.4.18 Data Justification Control
In most applications, the data transfer begins one serial clock cycle after the FS signal is sampled
active. This is the DCI module default. An alternate data alignment can be selected by setting the
DJST control bit (DCICON2<5>). When DJST = 1, data transfers will begin during the same
serial clock cycle as the FS signal.
22.4.19 DCI Module Interrupts
The frequency of DCI module interrupts is dependent on the number of active time slots (TSCON
and RSCON registers), length of the data frame (WS and COFSG control bits), and the BLEN
control bits. An interrupt is generated at the following times:
• When the buffer length has been reached
• When a frame boundary is reached
A buffer memory transfer takes place each time the above events occur. A buffer memory
transfer is defined as the time when the previously written TXBUF values are transferred to the
transmit buffer memory and new received values in the receive buffer memory are transferred
into the RXBUF registers.
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