© 2004 Microchip Technology Inc. DS70069C-page 22-15
Section 22. Data Converter Interface (DCI)
Data Converter
Interface (DCI)
22
22.4.11 Receive Slot Enable Bits
The RSCON SFR contains control bits (RSE<15:0>) that are used to enable up to 16 time slots
for reception. The size of each receive time slot is determined by the WS<3:0> control bits and
can vary from 4 to 16 bits.
If a receive time slot is enabled via one of the RSE bits (RSEx = 1), the Shift register contents
will be written to the current DCI receive buffer location and the buffer control logic will advance
to the next available buffer location.
Data is not packed in the receive memory buffer locations if the selected word size is less than
16 bits. Each received slot data word is stored in a seperate 16-bit buffer location. Data is always
stored in a left-justified format in the receive memory buffer.
22.4.12 TSCON and RSCON Operation with Buffer Control Unit
The slot enable bits in the TSCON and RSCON registers function independently, with the
exception of the buffer control logic. For each time slot in a data frame, the buffer location is
advanced if either the TSEx or the RSEx bit is set for the current time slot. That is, the buffer con-
trol unit synchronizes the Transmit and Receive buffering so that the Transmit and Receive buffer
location will always be the same for each time slot in the data frame.
If the TSEx bit and the RSEx bit are both set for every time slot that is used in the data frame,
the DCI will Transmit and Receive equal amounts of data .
In some applications, the number of data words transmitted during a frame may not equal the
number of words received. As an example, assume that the DCI is configured for a 2-word data
frame, TSCON = 0x0001 and RSCON = 0x0003. This configuration would allow the DCI to
transmit one data word per frame and receive two data words per frame. Since two data words
are received for each data word that is transmitted, the user would write every other transmit
buffer location. Specifically, only TXBUF0 and TXBUF2 would be used to transmit data.
Figure 22-6: DCI Buffer Operation: TSCON =
0x0001
, RSCON =
0x0003
, BLEN<1:0> =
11b
22.4.13 Receive Status Bits
There are two receive status bits, RFUL and ROV.
The receive status bits only indicate status for register locations that are enabled for use by the
module. This is a function of the BLEN<1:0> control bits. If the buffer length is set to less than
four words, the unused buffer locations will not affect the receive status bits.
The RFUL status bit (DCISTAT<2>) is read only and indicates that new data is available in the
Receive registers. The RFUL bit is cleared automatically when all RXBUF registers in use have
been read by the user software.
The ROV status bit (DCISTAT<3>) is read only and indicates that a receive overflow has
occurred for at least one of the Receive register locations. A receive overflow occurs when the
RXBUF register location is not read by the user software before new data is transferred from the
buffer memory. When a receive overflow occurs, the old contents of the register are overwritten.
The ROV status bit is cleared automatically when the register that caused the overflow is read.
Transmit Registers
TXBUF0
TXBUF1
TXBUF2
TXBUF3
Receive Registers
RXBUF0
RXBUF1
RXBUF2
RXBUF3
Note: User writes to TXBUF0 and TXBUF2. TXBUF1 and TXBUF3 not used by transmit logic.
Data Word #1
Data Word #2
Data Word #1
Data Word #2
Data Word #3
Data Word #4
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