Microchip Technology dsPIC30F - Page 580

dsPIC30F Family Reference Manual
DS70069C-page 22-14 © 2004 Microchip Technology Inc.
Figure 22-5: DCI Buffer Control Unit
22.4.10 Transmit Slot Enable Bits
The TSCON SFR has control bits that are used to enable up to 16 time slots for transmission.
These control bits are the TSE<15:0> bits. The size of each time slot is determined by the
WS<3:0> word size selection bits and can vary up to 16 bits.
If a transmit time slot is enabled via one of the TSE bits (TSEx = 1), the contents of the current
transmit buffer location will be loaded into the CSDO Shift register and the DCI buffer control unit
will increment to point to the next buffer location.
Not all TSE control bits will have an effect on the module operation if the selected frame size has
less than 16 data slots. The Most Significant TSE control bits are not used. For example, if
COFSG<3:0> = 0111 (8 data slots per frame), TSE8 through TSE15 will have no effect on the
DCI operation.
22.4.10.1 CSDO Mode Control
During disabled transmit time slots, the CSDO pin can drive ‘0’s or can be tri-stated, depending
on the state of the CSDOM bit (DCICON1<6>). A given transmit time slot is disabled if its
corresponding TSEx bit is cleared in the TSCON register.
If the CSDOM bit is cleared (default), the CSDO pin will drive ‘0’s onto the CSDO pin during
disabled time slot periods. This mode is used when there are only two devices (1 master and 1
slave) attached to the serial bus.
If the CSDOM bit is set, the CSDO pin will be tri-stated during unused time slot periods. This
mode allows multiple dsPIC30F devices to share the same CSDO line in a multiplexed
application. Each device on the CSDO line is configured so that it will only transmit data during
specific time slots. No two devices should transmit data during the same time slot.
Transmit Registers
Transmit Buffer
Buffer Transfer Signal
Receive Registers Receive Buffer
BLEN
Buffer Control
Receive
Buffer
Select
Transmit
Buffer
Select
DCI
RXBUF0
RXBUF1
RXBUF2
RXBUF3
TXBUF0
TXBUF1
TXBUF2
TXBUF3
4 4
2
4 4
Shift Register