© 2004 Microchip Technology Inc. DS70069C-page 22-13
Section 22. Data Converter Interface (DCI)
Data Converter
Interface (DCI)
22
22.4.7 Frame Synchronization Generator
The Frame Sync Generator (FSG) is a 4-bit counter that sets the frame length in data words. The
period for the FSG is set by writing the COFSG<3:0> control bits (DCICON2<8:5>). The FSG
period (in serial clock cycles) is determined by the following formula:
Equation 22-2: Frame Length, In CSCK Cycles
Frame lengths up to 16 data words may be selected. The frame length in serial clock periods will
vary up to a maximum of 256 depending on the word size that is selected.
22.4.8 Transmit and Receive Registers
The DCI has four Transmit registers, TXBUF0...TXBUF3, and four Receive registers,
RXBUF0..RXBUF3. All of the Transmit and Receive registers are memory mapped.
22.4.8.1 Buffer Data Alignment
Data values are always stored left-justified in the DCI registers, since audio PCM data is
represented as a signed 2’s complement fractional number. If the programmed DCI word size is
less than 16 bits, the unused LSbs in the Receive registers are set to ‘0’ by the module. Also, the
unused LSbs in the Transmit register are ignored by the module.
22.4.8.2 Transmit and Receive Buffers
The Transmit and Receive registers each have a set of buffers that are not accessible by the
user. Effectively, each transmit and receive buffer location is double-buffered. The DCI transmits
data from the transmit buffers and writes received data to the receive buffers. The buffers allow
the user to read and write the RXBUF and TXBUF registers, while the DCI uses data from the
buffers.
22.4.9 DCI Buffer Control Unit
The DCI module contains a buffer control unit that transfers data between the buffer memory and
the Serial Shift register. The buffer control unit also transfers data between the buffer memory
and the TXBUF and RXBUF registers. The buffer control unit allows the DCI to queue the
transmission and reception of multiple data words without CPU overhead.
The DCI generates an interrupt each time a transfer between the buffer memory and the TXBUF
and RXBUF registers takes place. The number of data words buffered between interrupts is
determined by the BLEN<1:0> control bits (DCICON2<11:10>). The size of the transmit and
receive buffering may be varied from 1 to 4 data words using the BLEN<1:0> bits.
Each time a data transfer takes place between the DCI Shift register and the buffer memory, the
DCI buffer control unit is incremented to point to the next buffer location. If the number of
transmitted or received data words is equal to the BLEN value + 1, the following will occur:
• The buffer control unit is reset to point to the first buffer location
• The received data held in the buffer is transferred to the RXBUF registers
• The data in the TXBUF registers is transferred to the buffer
• A CPU interrupt is generated
The DCI buffer control unit will also reset the buffer pointer to the first buffer location each time a
frame boundary is reached. This action ensures alignment between the buffer locations and the
enabled time slots in the data frame.
The DCI buffer control unit always accesses the same relative location in the Transmit and
Receive buffers. If the DCI is transmitting data from TXBUF3, for example, then any data
received during that time slot will be written to RXBUF3.
FrameLength = (WS<3:0> + 1) • (COFSG<3:0> + 1)
Note: The COFSG control bits will have no effect in AC-Link mode, since the frame length
is set to 256 serial clock periods by the protocol.
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