dsPIC30F Family Reference Manual
DS70069C-page 22-12 © 2004 Microchip Technology Inc.
22.4.3 Bit Clock Generator
The DCI module has a dedicated 12-bit time base that produces the bit clock. The bit clock rate
(period) is set by writing a non-zero 12-bit value to the BCG<11:0> control bits
(DCICON3<11:0>). When the BCG<11:0> bits are set to zero, the bit clock will be disabled.
When the CSCK pin is controlled by the DCI module, the corresponding PORT, LAT and TRIS
Control register values for the CSCK pin will be overridden and the data direction for the CSCK
pin will be controlled by the CSCKD control bit (DCICON1<10>).
If the serial clock for the DCI is to be provided by an external device, the BCG<11:0> bits should
be set to ‘0’ and the CSCKD bit set to ‘1’.
If the serial clock is to be generated by the DCI module, the BCG<11:0> control bits should be
set to a non-zero value (see Equation 22-1) and the CSCKD control bit should be set to zero.
The formula for the bit clock frequency is given in Equation 22-1.
Equation 22-1: DCI Bit Clock Generator Value
The required bit clock frequency will be determined by the system sampling rate and frame size.
Typical bit clock frequencies range from 16x to 512x the converter sample rate, depending on
the data converter and the communication protocol that is used.
22.4.4 Sample Clock Edge Selection
The CSCKE control bit (DCICON1<9>) determines the sampling edge for the serial clock signal.
If the CSCKE bit is cleared (default), data will be sampled on the falling edge of the CSCK signal.
The AC-Link protocols and most multi-channel formats require that data be sampled on the
falling edge of the CSCK signal. If the CSCKE bit is set, data will be sampled on the rising edge
of CSCK. The I
2
S protocol requires that data be sampled on the rising edge of the serial clock
signal.
22.4.5 Frame Sync Mode Control Bits
The type of interface protocol supported by the DCI is selected using the COFSM<1:0> control
bits (DCICON1<1:0>). The following Operating modes can be selected:
• Multi-channel Mode
•I
2
S Mode
• AC-Link Mode (16-bit)
• AC-Link Mode (20-bit)
Specific information for each of the protocols is provided in subsequent sections.
22.4.6 Word-Size Selection Bits
The WS<3:0> word-size selection bits (DCICON2<3:0>) determine the number of bits in each
DCI data word. Any data length from 4 to 16 bits may be selected.
Note: The CSCK I/O pin will be controlled by the DCI module if the DCIEN bit is set OR
the bit clock generator is enabled by writing a non-zero value to BCG<11:0>. This
allows the bit clock generator to be operated independently of the DCI module.
BCG<11:0> =
f
CY
2 fCSCK
– 1
Note: The BCG<11:0> bits have no effect on the operation of the DCI module when the
CSCK signal is provided externally (CSCKD = 1).
Note: The WS control bits are used only in the multi-channel and I
2
S modes. These bits
have no effect in AC-Link mode since the data slot sizes are fixed by the protocol.
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