© 2004 Microchip Technology Inc. DS70069C-page 22-11
Section 22. Data Converter Interface (DCI)
Data Converter
Interface (DCI)
22
22.4.1 DCI Pins
There are four I/O pins associated with the DCI. The DCI, when enabled, controls the data
direction of each of the four pins.
22.4.1.1 CSCK Pin
The CSCK pin provides the serial clock connection for the DCI. The CSCK pin may be configured
as an input or output using the CSCKD control bit, DCICON1<10>. When the CSCK pin is
configured as an output (CSCKD = 0), the serial clock is derived from the dsPIC30F system clock
source and supplied to external devices by the DCI. When the CSCK pin is configured as an input
(CSCKD = 1), the serial clock must be provided by an external device.
22.4.1.2 CSDO Pin
The Serial Data Output (CSDO) pin is configured as an output only pin when the module is
enabled. The CSDO pin drives the serial bus whenever data is to be transmitted. The CSDO pin
can be tri-stated or driven to ‘0’ during serial clock periods when data is not transmitted, depend-
ing on the state of the CSDOM control bit (DCICON1<6>). The tri-state option allows other
devices to be multiplexed onto the CSDO connection.
22.4.1.3 CSDI Pin
The serial data input (CSDI) pin is configured as an input only pin when the module is enabled.
22.4.1.4 COFS Pin
The frame synchronization (COFS) pin is used to synchronize data transfers that occur on the
CSDO and CSDI pins. The COFS pin may be configured as an input or an output. The data direc-
tion for the COFS pin is determined by the COFSD control bit (DCICON1<8>). When the COFSD
bit is cleared, the COFS pin is an output. The DCI module will generate frame synchronization
pulses to initiate a data transfer. The DCI is the master device for this configuration. When the
COFSD bit is set, the COFS pin becomes an input. Incoming synchronization signals to the
module will initiate data transfers. The DCI is a slave device when the COFSD control bit is set.
22.4.2 Module Enable
The DCI module is enabled or disabled by setting/clearing the DCIEN control bit
(DCICON1<15>). Clearing the DCIEN control bit has the effect of resetting the module. In
particular, all counters associated with serial clock generation, frame sync, and the buffer control
logic are reset (see Section 22.5.1.1 “DCI Start-up and Data Buffering” and Section
22.5.1.2 “DCI Disable” for additional information).
When enabled, the DCI controls the data direction for the CSCK, CSDI, CSDO and COFS I/O
pins associated with the module. The PORT, LAT, and TRIS register values for these I/O pins are
overridden by the DCI module when the DCIEN bit is set.
It is also possible to override the CSCK pin separately when the bit clock generator is enabled.
This permits the bit clock generator to be operated without enabling the rest of the DCI module.
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