© 2004 Microchip Technology Inc. DS70069C-page 22-19
Section 22. Data Converter Interface (DCI)
Data Converter
Interface (DCI)
22
22.5.1.2 DCI Disable
The DCI module is disabled by clearing the DCIEN control bit (DCICON1<15>). When the DCIEN
bit is cleared, the module will finish the current data frame transfer that is in progress. An interrupt
will be generated if the transmit/receive buffers need to be written/read before the end of the
frame.
The DCIEN bit must be cleared at least 3 CSCK cycles before the end of the frame disables the
module at that frame. If not, the module will disable on the next frame.
The DCI will not generate any further frame sync pulses after the DCIEN bit is cleared, nor will it
respond to an incoming frame sync pulse.
When the frame sync generator has reached the final time slot in the data frame, all state
machines associated with the DCI will be reset to their Idle state and control of the I/O pins asso-
ciated with the module will be released. The user may poll the SLOT<3:0> status bits
(DCISTAT<11:7>) after the DCIEN bit is cleared to determine when the module is Idle. The DCI
is Idle when SLOT<3:0> = 0000b and DCIEN = 0.
When the module enters the Idle state, any data in the Receive Shadow registers will be
transferred to the RXBUF registers, and the RFUL and ROV status bits will be affected
accordingly.
Figure 22-8: DCI Timing, Module Disable
3
CSCK
Data 2 1 0 3 2103 2103 210
DCIEN
COFS
3 210
0011 0000 0001 0010 0011 0000SLOT
RFUL
WS = 0011b
COFSG = 0011b
FS pulse not
generated.
Receive buffer contents
transferred to RXBUF.
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