dsPIC30F Family Reference Manual
DS70069C-page 22-20 © 2004 Microchip Technology Inc.
22.5.2 Master vs. Slave Operation
The DCI can be configured for master or slave operation. The master device generates the frame
sync signal to initiate a data transfer. The Operating mode (master or slave) is selected by the
COFSD control bit (DCICON1<8>).
When the DCI module is operating as a master device (COFSD = 0), the COFSM mode bits
determine the type of frame sync pulse that is generated by the frame sync generator logic. A
new frame synchronization signal is generated when the frame sync generator resets and is
output on the COFS pin.
When the DCI module is operating as a frame sync slave (COFSD = 1), data transfers are
controlled by the device attached to the DCI module. The COFSM control bits control how the
DCI module responds to incoming FS signals.
In the Multi-Channel mode, a new data frame transfer will begin one serial clock cycle after the
COFS pin is sampled high. The pulse on the COFS pin resets the frame sync generator logic.
In the I
2
S mode, a new data word will be transferred one serial clock cycle after a low-to-high or
a high-to-low transition is sampled on the COFS pin. A rising or falling edge on the COFS pin
resets the frame sync generator logic.
In the AC-Link mode, the tag slot and subsequent data slots for the next frame will be transferred
one serial clock cycle after the COFS pin is sampled high.
The COFSG and WS bits must be configured to provide the expected frame length when the
module is operating in the Slave mode. Once a valid frame sync pulse has been sampled by the
module on the COFS pin, an entire data frame transfer will take place. The module will not
respond to further frame sync pulses until the current data frame transfer has fully completed.
22.5.3 Data Packing for Long Data Word Support
Many codecs have data word lengths in excess of 16 bits. The DCI natively supports word
lengths up to 16 bits, but longer word lengths can be supported by enabling multiple Transmit
and Receive slots and packing data into multiple transmit and receive buffer locations. For
example, assume that a particular codec transmits/receives 24-bit data words. This data could
be transmitted and received by setting BLEN<1:0> = 01b (two data words per interrupt) and
setting TSCON = RSCON = 0x0003. This will enable transmission and reception during the first
two time slots of the data frame. The 16 MSbs of the transmit data are written to TXBUF0. The
8 LSbs of the transmit data are written left-justified to TXBUF1 as shown in Figure 22-9. The 8
LSbs of TXBUF1 can be written to ‘0’. The 24-bit data received from the codec will be loaded into
RXBUF0 and RXBUF1 with the same format as the transmit data.
Any combination of word size and enabled time slots may be used to transmit and receive long
data words in multiple Transmit and Receive registers. For example, the 24 bit data word
example shown in Figure 22-9 could be transmitted/received in three consecutive registers by
setting WS<3:0> = 0111 (word size = 8 bits), BLEN<1:0> = 10 (buffer three words between
interrupts), and TSCON = RSCON = 0x0007 (transmit/receive during the first three time slots of
the data frame). Each Transmit and Receive register would contain 8 bits of the data word.
Figure 22-9: Data Packing Example for Long Data Words
Transmit Registers
TXBUF0
TXBUF1
TXBUF2
TXBUF3
Data Word bits 24:8
000000000
bits 7:0
TSCON = RSCON = 0x0003
BLEN<1:0> = 01b
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