© 2004 Microchip Technology Inc. DS70069C-page 22-21
Section 22. Data Converter Interface (DCI)
Data Converter
Interface (DCI)
22
22.5.4 Multi-Channel Operation
The Multi-Channel mode (COFSM<1:0> = 00) is used for codecs that require a frame sync pulse
that is driven high for one serial clock period to initiate a data transfer. One or more data words
can be transferred in the data frame. The number of clock cycles between successive frame sync
pulses will depend on the device connected to the DCI module. A timing diagram for the frame
sync signal in Multi-Channel mode is shown in Figure 22-10. A timing example, indicating a
four-word data transfer is also shown in Figure 22-2.
Figure 22-10: Frame Sync Timing, Multi-Channel Mode
22.5.4.1 Multi-Channel Setup Details
The steps required to configure the DCI for a codec using the Multi-Channel mode are provided
in this section. This Operating mode can be used for codecs with one or more data channels.
The setup is similar regardless of the number of channels.
For this setup example, a hypothetical codec will be considered. The single channel codec used
for this setup example will use a 256 fs serial clock frequency with a 16-bit data word transmitted
at the beginning of each frame.
The steps required for setup and operation are described below.
1. Determine the sample rate and data word size required by the codec. An 8 kHz sampling
rate is assumed for this example.
2. Determine the serial transfer clock frequency required by the codec. Most codecs require
a serial clock signal that is some multiple of the sampling frequency. The example codec
requires a frequency that is 256 fs, or 1.024 MHz. Therefore, a frame sync pulse must be
generated every 256 serial clock cycles to start a data transfer.
3. The DCI must be configured for the serial transfer clock. If the CSCK signal will be
generated by the DCI, clear the CSCKD control bit (DCICON1<10>) and write a value to
DCICON3 that will produce the correct clock frequency (See Section 22.4.3 “Bit Clock
Generator”). If the CSCK signal is generated by the codec or other external source, set
the CSCKD control bit and clear the DCICON3 register.
4. Clear the COFSM<1:0> control bits (DCICON1<1:0>) to set the frame synchronization
signal to Multi-Channel mode.
5. If the DCI will generate the frame sync signal (master), then clear the COFSD control bit
(DCICON1<8>). If the DCI will receive the frame sync signal (slave), then set the COFSD
control bit.
6. Clear the CSCKE control bit (DCICON1<9>) to sample incoming data on the falling edge
of CSCK. This is the typical configuration for most codecs. Refer to the codec data sheet
to ensure the correct sampling edge is used.
7. Write the WS<3:0> control bits (DCICON2<3:0>) for the desired data word size. The
example codec requires WS<3:0> = 1111b for a 16-bit data word size.
CSCK
Data
COFS
MSB LSB
Frame Synch Sampled Here
First Data Bit Sampled Here
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