dsPIC30F Family Reference Manual
DS70069C-page 22-22 © 2004 Microchip Technology Inc.
8. Write the COFSG<3:0> control bits (DCICON2<8:5>) for the desired number of data
words per frame. The WS and COFSG control bits will determine the length of the data
frame in CSCK cycles (see Section 22.4.7 “Frame Synchronization Generator”)
COFSG<3:0> = 1111b is used for this codec to provide the 256-bit data frame required
by the example codec.
9. Set the Output mode for the CSDO pin using the CSDOM control bit (DCICON1<6>). If a
single device is attached to the DCI, CSDOM can be cleared. This will force the CSDO pin
to ‘0’ during unused data time slots. You may need to set CSDOM if multiple devices are
attached to the CSDO pin.
10. Write the TSCON and RSCON registers to determine which data time slots in the frame
are to be transmitted and received, respectively. For this single channel codec, use
TSCON = RSCON = 0x0001 to enable transmission and reception during the first 16-bit
time slot of the data frame.
11. Set the BLEN control bits (DCICON2<11:10>) to buffer the desired amount of data words.
For the single channel codec, BLEN = 00 will provide an interrupt at each data frame. A
higher value of BLEN could be used for this codec to buffer multiple samples between
interrupts.
12. If interrupts are to be used, clear the DCIIF status bit (IFS2<9>) and set the DCIIE control
bit (IEC2<9>).
13. Begin operation as described in Section 22.5.1.1 “DCI Start-up and Data Buffering”.
22.5.5 I
2
S Operation
The I
2
S Operating mode is used for codecs that require a frame sync signal that has a 50% duty
cycle. The period of the I
2
S frame sync signal in serial clock cycles is determined by the word
size of the codec that is connected to the DCI module. The start of a new word boundary is
marked by a high-to-low or a low-to-high transition edge on the COFS pin as shown in
Figure 22-11. I
2
S codecs are generally stereo or two-channel devices, with one data word
transferred during the low time of the frame sync signal and the other data word transmitted
during the high time.
Figure 22-11: I
2
S Interface Frame Sync Timing
The DCI module is configured for I
2
S mode by writing a value of 01h to the COFSM<1:0> control
bits in the DCICON1 SFR. When operating in the I
2
S mode, the DCI module will generate frame
synchronization signals with a 50% duty cycle. Each edge of the frame synchronization signal
marks the boundary of a new data word transfer. Refer to the Appendix of this manual for more
information about the I
2
S protocol. The user must also select the frame length and data word size
using the COFSG and WS control bits in the DCICON2 SFR.
Note: A 5-bit transfer is shown here for illustration purposes. The I
2
S protocol does not specify
word length, this will be system dependent.
MSB LSB MSB LSB
CSCK
Data
COFS
Frame Synch Edge Sampled
First Data Bit Sampled
To Next Page
Loading...
