© 2004 Microchip Technology Inc. DS70069C-page 22-23
Section 22. Data Converter Interface (DCI)
Data Converter
Interface (DCI)
22
22.5.5.1 I
2
S Setup Details
The steps required to configure the DCI for an I
2
S codec are provided in this section. For this
setup example, a hypothetical I
2
S codec will be considered.
The I
2
S codec in this setup example will use a 64 fs serial clock frequency, with two 16 bit data
words during the data frame. Therefore, the frame length will be 64 CSCK cycles, with the COFS
signal high for 32 cycles and low for 32 cycles. The first data word will be transmitted one CSCK
cycle after the falling edge of COFS, and the second data word will be transmitted one CSCK
cycle after the rising edge of COFS as shown in Figure 22-11.
1. Determine the sample rate used by the codec to determine the CSCK frequency. It is
assumed in this example that fs is 48 kHz.
2. Determine the serial transfer clock frequency required by the codec. The example codec
requires a frequency that is 64 fs, or 3.072 MHz.
3. The DCI must be configured for the serial transfer clock. If the CSCK signal will be gener-
ated by the DCI, clear the CSCKD control bit (DCICON1<10>) and write a value to
DCICON3 that will produce the correct clock frequency (see Section 22.4.3 “Bit Clock
Generator”). If the CSCK signal is generated by the codec or other external source, set
the CSCKD control bit and clear the DCICON3 register.
4. Next, set COFSM<1:0> = 01b to set the frame synchronization signal to I
2
S mode.
5. If the DCI will generate the frame sync signal (master), then clear the COFSD control bit
(DCICON1<8>). If the DCI will receive the frame sync signal (slave), then set the COFSD
control bit.
6. Set the CSCKE control bit (DCICON1<9>) to sample incoming data on the rising edge of
CSCK. This is the typical configuration for most I
2
S codecs.
7. Write the WS<3:0> control bits (DCICON2<3:0>) for the desired data word size. For the
example codec, use WS<3:0> = 1111b for a 16-bit data word size.
8. Write the COFSG<3:0> control bits (DCICON2<8:5) for the desired number of data words
per frame. The WS and COFSG control bits will determine the length of the data frame in
CSCK cycles (see Section 22.4.7 “Frame Synchronization Generator”). For this exam-
ple codec, set COFSG<3:0> = 0001b.
9. Set the Output mode for the CSDO pin using the CSDOM control bit (DCICON1<6>). If a
single device is attached to the DCI, CSDOM can be cleared. You may need to set
CSDOM if multiple devices are attached to the CSDO pin.
10. Write the TSCON and RSCON registers to determine which data time slots in the frame
are to be transmitted and received, respectively. For this codec, set TSCON = 0x0001
and RSCON = 0x0001 to enable transmission and reception during the first 16-bit time
slot of the 32-bit data frame. Adjacent time slots can be enabled to buffer data words
longer than 16 bits.
11. Set the BLEN<1:0> control bits (DCICON2<11:10>) to buffer the desired amount of data
words. For a two-channel I
2
S codec, BLEN<1:0> = 01b will generate an interrupt after
transferring two data words.
12. If interrupts are to be used, clear the DCIIF status bit (IFS2<9>) and set the DCIIE control
bit (IEC2<9>).
13. Begin operation as described in Section 22.5.1.1 “DCI Start-up and Data Buffering”. In
the I
2
S Master mode, the COFS pin will be driven high after the module is enabled and
begin transmitting the data loaded in TXBUF0.
Note: In the I
2
S mode, the COFSG bits are set to the length of 1/2 of the data frame. For
this example codec, set COFSG<3:0> = 0001b (two data words per frame) to
produce a 32-bit frame. This will produce an I
2
S data frame that is 64 bits in length.
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